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I would guess that in some cases where ACC creates more stability its due to a shortcoming of the MB. When ACC is enabled from what I understand, the clock is generated off of a diffrent PLL and accesses the die by a different circuit. If the boards default clockgen and circuits are not up to 100% perfect in function and the ACC southbridge clockgen is, it could make a large impact on stability.
I would also speculate that its threw this other link from the southbridge that is accessing the fused off cores and cache that aparently were only fused off from the default link.
This of course is all just speculation.
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