@Extelleron

~20 men team was assigned for Brisbane shrink of Windsor core.They did the job fine and in record time.Granted G1 wasn't perf. braker due to L2 cache latency that was a bit higher than in F3,plus it had 512KB of L2 per core,but it was done quite easily and with very small R&D. Same think can happen with 32nm K10.5 shrink since AMD has already done it with Shanghai(they had 10 smaller teams all around the world designing and optimizing various parts of the MPU,thus cutting time considerably). As you can see from G2 and C2 examples,MPU shrink is not that hard thing to do,especially if it could help you a lot in understanding the node that you will use for your new generation uarchitecture. I hope you can see now how "Orochi" and "first 32nm CPU" doesn't go in the same sentence.

Quote Originally Posted by Vozer View Post
Hmm... but their latest official roadmap indicates that they will.

Do you have any proof to back what you said?
Their last roadmap is the vaguest of all.If you believe they will risk the company's future by launching a new design on a new process node,suit yourself.