**Official DFI LanParty UT X48-T2R(and LT) Discussion

[zanzabar]

set it to the lowest one its like 100.23%

[JohnEJohn]

Sorry for the ignorance but what exactly does this do?

From what I have read it adds a slight more voltage when under load, if this is incorrect then please correct me

If I do this should I reduce any voltages?

TIA

[zanzabar]

its a voltage multi for the cpu core and with it on auto it will overvolt your cpu, 100.23% means that u will have 100.23% of what u set the vcore to

[JohnEJohn]

Thanks for that, will now set it back.

Is there any other advice you could give me based on the settings or anything you think I have done worng or could be improved?

My last system was an opteron 175 which is still going strong at 2.85 GHz 3 years later
Things have changed a lot since then and many of these settings are new to me.

This board/gen is certaintly a lot different to my old ASUS a8n-sli/opty

[RGone]

From what I have read it adds a slight more voltage when under load, if this is incorrect then please correct me = consider yourself corrected then. CPU VID is Vcore setting. CPU SPECIAL ADD will add a % of voltage TO the Vcore setting at any and all times.

[JohnEJohn]

Yeah thanks for that but it was already explained to me.
I don't mind being corrected which is why I asked.

Thanks

[seba84_2005]

Hey guys

I have small problem I can not overclock my Q9550 to 4GHz. Try sett this settings

Clock VCO Divider Auto
CPU Clock Ratio 8.5x
CPU N/2 Ratio Enabled
Target CPU Clock 4037MHz
CPU Clock 475 MHz
Boot Up Clock 100 MHz
Dram speed 400/1066
PCIE clock 110 MHz
PCIE Slot Config 4x NC
CPU Spread Spectrum Disabled
PCIE Spread Spectrum Disabled
SATA Spred Spectrum Disabled
Cpu Feature Multicore Enabled
Rest Disabled

Voltage Settings
CPU VID Control 1.4v
CPU VID Specail Add Limit Enabled
CPU VID Specail Add Auto
Dram Voltage Control 2.23v
SB Core/CPU Pll Voltage auto
NB Core Voltage 1.47v
Vcore Droop Control Enabled
Clockgen Voltage Control 3.60v
GTL+ Buffers Strength Strong
Host Skew Rate Weak
GTL Ref Control Disable

Dram Timing
Enhance Data Transmitting Normal
Enhance Addressing Normal
T2 Dispatch Enabled
TCL 5
TRCD 5
TRP 5
TRAS 18
All other Values Auto/Default
Read Delay Phase Adjust Auto/Default
Clock Setting Fine Delay
Dram Clock Driving Strength Level 6
Dram Data Driving Strength Level 8
CH1 DLL Default Skew Model Model 0
CH2 DLL Default Skew Model Model 0
Fine Delay Step Degree 5PS
All other Values Auto/Default

PLL 1.6v
VTT 1.31v

change CPU voltage from 1.3625v to 1.42v system not post, freeze on startup logo windows vista what maybe not so

[SNiiPE_DoGG]

raise your vtt to 1.45

also drop PCIE clock to 105 or lower, you'll literally kill your hard drives with that frequency

[=[PULSAR]=]

I'm going to post in the for sale section as soon as my new hardware gets in, but heads up I'm going to be selling my X48-T2R if anyone is interested.

[lupo17]

hi there, I'm new to DFI, so take me as a newbee [after 3 days of browsing the net, exploring the bios...setting and resetting, I admit that I've falled here from stone-age...in one word...I'm an ex-asus...]

my rig > DFI-UT-X48-T2R / E8600 / 4x1_Team-Xtreem_8500_[D9__] / HIS-4850 / ps-antec-650w

could someone [with a similar config, please] share with me some .abs file with a 24/7 settings... [I'm aiming at fsb500...for not missingtoo much my last P45-Asus / with mems at 5:6 ]
tks

[mikeyakame]

Heres a little info I worked out from the LT-X48-T2R i bought as a toy to play with

Host Clock Slew Rate
MCH Slew Rate Voltage Reference Points
Best behaviour should occur when all 3 are raised by same value, more important Vref1 and Vref2 should be the same. Vref3 should be raised by same as Vref1/2 but slightly less or slightly more might be beneficial at high FSB to help with slew rate matching between high and low clock.

Vref1 and Vref2 I'm pretty sure set the FSB_SWING Overdrive Region on either side of the crossing point, within Overdrive region clock edge flight time is calculated roughly and slew rate is matched between the driver and the receiver. Also matching is performed against the inverted differential clock opposing edge.

MCH Vref1 = AGTL+ Slew Rate Voltage Ref High at Receiver [ Vref3 + 200mV ], FSB_SWING Clock# to Clock (low clock to high clock), base = 00h
MCH Vref2 = AGTL+ Slew Rate Voltage Ref Low at Receiver [ Vref3 - 200mv ], FSB_SWING Clock to Clock# (high clock to low clock), base = 00h
MCH Vref3 = AGTL+ Slew Rate Voltage Ref at Driver (receiver references are calculated from this unless the slew rate of Voltage Out at the receiver is too fast or slow, then Vref1/2 offsets are used to calculate approx edge rate of the clock), base = 80h

MCH Ron = Slew Rate Resistance On, determines how long pins are held when switching between pull-up and pull-down drivers. The flat clock edge period is determined by this, longer hold time can be used to compensate against rising clock edge slew rate being too slow, and falling clock edge slew rate being too fast. Slew rate is V/ns, voltage per nanosecond.

MCH Rtt = Slew Rate Pull-up Resistance, determines rising and falling clock edge rates.
* lower Rtt gives slower rising clock edge rate and faster falling clock edge rate
* higher Rtt gives faster rising clock edge rate and slower falling clock edge rate
* since ringback is a problem on the rising clock edge due to Voltage out being pulled up to Vtt, we can assume this is a negative Rtt Offset as Intel engineers are much too smart to design a positive offset that has no real world gains!

MCH Slew Rate Offset = I think this is an adjustment offset for Voltage Out at the driver to offset against signal loss at the input buffer of the receiver


These values become highly important and valuable as you get closer to hitting your FSB Wall. Understanding their place is just trial and error. Change one at a time and note down any changes you notice even slightly

DRAM Drive Strength/Delay Locked Loop Skew Models (DLL)

I've got G.Skill PC2-8800 PI 2x2GB sticks running on this board in Dimm2/4 as DLL skew models seem to work best with 2GB sticks like this from what I've found.

Default DLL Model is 0, Default DRAM CK (clock) Drive Strength is 6, Default DRAM DQ (data) Drive Strength is 8.

Best values I've found for these are.

DRAM CK Drive Strength = 4
DRAM DQ Drive Strength = 5
DRAM DLL Model CHA = 1
DRAM DLL Model CHB = 2

Fine clock adjust = 25ps

Cross Clocking Skew CHA = More aggressive
*Dimm2 Fine Clock Delay = 575ps
*Dimm2 Fine Control Delay = Current
*Dimm2 Fine Command Delay = 275ps

Cross Clocking Skew CHB = More aggressive
*Dimm4 Fine Clock Delay = 500ps
*Dimm4 Fine Control Delay = Current
*Dimm4 Fine Command Delay = 250ps

Common Clock Skew CHA/CHB = More Aggressive

Skew between CHA & CHB should be no more than 60-70ps unless there is heavy signal degradation at high fsb/dram clock. Between Dimm1/2 and Dimm3/4 in each channel, no more than 25-35ps skew.

[terroristone]

you just lost me, way over my head dude.

[mikeyakame]

you just lost me, way over my head dude.

I'll explain it a little easier to understand when I get enough consistent results to correlate with the theory

Simply put they are registers used for Host BCLK edge rate flight time calculation. In other words Host slew rate, the rate at which the clock edge rises and falls in Voltage/nanosecond. There are base reference points and resistor impedance which have been chosen by design for the working frequency of the FSB of a board. Problem is that once we go past a certain point, on the LT/UT T2R it's probably around 420-430Mhz FSB with a quad core. '

Vref offsets are for compensating for noise, ringback at the receiver, and the voltage crossing point shifting outside of the working range of the compensation circuitry and Vtt playing a part in this as well as it gets higher and higher

By moving the point we expect the high clock and low clock# to cross over (voltage crossing point), and also offseting each "overdrive region" reference voltage, (the 0.2V region either side of the voltage crossing point), the MCH becomes able to more accurately do BCLK edge rate estimation, which as FSB gets further past 400mhz becomes increasingly critical.

Higher FSB frequency means clock period becomes smaller, so without any kind of adjustment we hit a wall eventually when a FSB won't POST. As we approach this point by having access to these confusing as hell bios options we can bring the system back into similar tolerances if not better, as original at the expense of each set of values as they get higher their working FSB range gets lesser and lesser.

Enough about that.

I spent the last few days mucking around with DRAM DLL Default Skew Models and DRAM CLK / DQ Drive Strength values with my G.Skill PC2-8800PI 2x2GB sticks, which use Powerchip low voltage ICs still I believe.

I've come to the conclusion that the following 2 sets of values are suited best to these sticks.

DRAM CLK Drive Strength / DRAM Data Drive Strength / DRAM DLL Default Skew Model CH1 / DRAM DLL Default Skew Model CH2

3/6/5/5 and 4/7/6/6
for most clock speeds upto around 1155-1160mhz 5-5-5-15 2.01v

4/6/4/4
I found gave no errors at 1165mhz on my sticks, with ch1/ch2/common clock cross clocking skews set to aggressive, and tRRD=4, tRTP=4, tRDWR=9

Model 0 works best with ICs that do aggressive CAS timings while very clean on die termination for data strobing.
Model 4 is somewhere in the middle, neutral CAS and so so data strobing, most likely 2gb sticks with 8 ranks.
Model 7 is what appears to the have the weakest skew model most likely for poorly binned or high latency ics.

Ultimately from what I've observed, the best way to figure out the right Skew Models is to run with default bios settings, base FSB and say 800 or 1066mhz DDR2, or 1066 or 1333mhz DDR3 and have all cross clocking on auto/delays on current, and try each different model pair. The optimal values for your memory will generally be when the bios calculates Fine Clock Delay for channel 1 memory slot to be around 300-400ps, Fine Control Delay around 700-800ps for channel 1, and fine command delay 70-100ps higher than Fine Control Delay.

When switching between models safest way is to clear cmos, then set new Skew Model pair. Otherwise the bios calculations can be corrupted and give you a headache of a time of what shouldn't be nearly that bad. If you see Fine Control or Fine Command Delay for Either channel with a value smaller than 90-100ps or they vary greatly from channel 1 to 2 then the calculations were corrupted, clear cmos before you try again or you end up chasing your tail like a dog!

[terroristone]

so basicly these are the settings (along with gtl) are what need's to be played with when shooting for high FSB on a quad?
Andrew

[mikeyakame]

so basicly these are the settings (along with gtl) are what need's to be played with when shooting for high FSB on a quad?
Andrew

yep that sums it up mate

GTL References are used for common clock address strobe centre alignment, data strobe edge alignment, and determining logic high/low correctly so as to not read inverted data from logic low clock edge as non-inverted data from logic high clock edge so as to not invert 0 as 1 when 0 is 0 on logic high, or 1 as 1 when 1 is 0 on inverted logic low if differental clock voltage under or overshoots back inside overdrive region.

Where as MCH Vref references are external to AGTL+ bus, and are for FSB AGTL+ differential clock slew rate matching to Host BCLK slew rate, so that during MCH/DRAM cross clocking (read delay) DRAM DDR delay locked loop skews (from FSB AGTL+ clock on NB) and DRAM DQS (data strobe) can be phase aligned to FSB AGTL+ clock by means of Host BCLK clock gen reference which is same clock reference FSB is driven to.

Vref1-3 give additional offset compensation against Host BCLK reference for FSB clock, to shift voltage crossing point Vref3 higher or lower, and add offsets to Vref1 and Vref2 to correctly calculate Vref3,

If Vref1 at Vref+200mV is used when slew rate at receiver is too slow and voltage crossing couldnt be accurately determined to increase slew rate speed by extrapolating back to Vref3.

If Vref2 at Vref-200mV (previous Vref point) is used to calculate voltage crossing point Vref3 after the voltage has crossed Vref +- 200mv, and it undershoots or overshoots back within the overdrive region, new Vref3 is calculated to extrapolate correct slew rate leaving the overdrive region.

As you offset Vref3, apply same to Vref1 and Vref2 to make sure that in all scenarios Vref3 voltage crossing point reference calculation comes back the same offset you set at Vref3, so that FSB clock slew rate is matched to Host BCLK reference, and that it also matches slew rate of DRAM clock, CPU clock, PCIE clock, etc for common clock address strobes.

These help break an FSB wall because the wall exists when the circuit design can no longer stay within minimum requirements for FSB clock period stability and validity.

[deadman'sclick]

yep that sums it up mate

GTL References are used for common clock address strobe centre alignment, data strobe edge alignment, and determining logic high/low correctly so as to not read inverted data from logic low clock edge as non-inverted data from logic high clock edge so as to not invert 0 as 1 when 0 is 0 on logic high, or 1 as 1 when 1 is 0 on inverted logic low if differental clock voltage under or overshoots back inside overdrive region.

Where as MCH Vref references are external to AGTL+ bus, and are for FSB AGTL+ differential clock slew rate matching to Host BCLK slew rate, so that during MCH/DRAM cross clocking (read delay) DRAM DDR delay locked loop skews (from FSB AGTL+ clock on NB) and DRAM DQS (data strobe) can be phase aligned to FSB AGTL+ clock by means of Host BCLK clock gen reference which is same clock reference FSB is driven to.

Vref1-3 give additional offset compensation against Host BCLK reference for FSB clock, to shift voltage crossing point Vref3 higher or lower, and add offsets to Vref1 and Vref2 to correctly calculate Vref3,

If Vref1 at Vref+200mV is used when slew rate at receiver is too slow and voltage crossing couldnt be accurately determined to increase slew rate speed by extrapolating back to Vref3.

If Vref2 at Vref-200mV (previous Vref point) is used to calculate voltage crossing point Vref3 after the voltage has crossed Vref +- 200mv, and it undershoots or overshoots back within the overdrive region, new Vref3 is calculated to extrapolate correct slew rate leaving the overdrive region.

As you offset Vref3, apply same to Vref1 and Vref2 to make sure that in all scenarios Vref3 voltage crossing point reference calculation comes back the same offset you set at Vref3, so that FSB clock slew rate is matched to Host BCLK reference, and that it also matches slew rate of DRAM clock, CPU clock, PCIE clock, etc for common clock address strobes.

These help break an FSB wall because the wall exists when the circuit design can no longer stay within minimum requirements for FSB clock period stability and validity.

nice 1, these settings need sum clarification.

ive just read through ur posts & will need to many more times to fully understand it it is 2.30am atm & im half asleep.

thanks alot for all the info tho mikeyakame tho (legend)

regards

gm

[mikeyakame]

http://www.intel.com/design/PentiumI...s/24508601.pdf

If you are interested, take a read of this! It's probably the best documentation I've found describing AGTL+ design! It's a little old, but most design specs haven't changed all that much. It's a good read when you've got some spare time anyway!

[Shiranui Gen-An]

Lowest price I've seen for this board in the US: http://www.newegg.com/Product/Produc...DFI-_-13136049

[repsol_23]

Lowest price I've seen for this board in the US: http://www.newegg.com/Product/Produc...DFI-_-13136049

I should be getting my LT version from the egg today sometime. I saw it for less than $200 shipped so I jumped at the opportunity for running crossfire. I am currently using an Abit P35 Pro running an X6800 @ 3.8 Ghz with a FSB of 540 Mhz with a 1 Gb HD 4870. I hope I won't be dissappointed with this board. I know I may have some difficulties running the same FSB as before but I am really looking forward to getting another 4870 for crossfire.

Is there any advice anyone out there can give me for overclocking and bios settings? I have read just about every post here (took a several days) and have absorbed as much info as I can already. Any advice would be greatly appreciated. Thanks!!

[Shiranui Gen-An]

I just won an open box UT X48 from NCIX on ebay, I'll have three DFI boards now

[zsamz_]

I just won an open box UT X48 from NCIX on ebay, I'll have three DFI boards now

if you got a ut p35 u wasted ur money

[karateo]

He WON the motherboard

[Shiranui Gen-An]

if you got a ut p35 u wasted ur money

UT P35 isn't working too well with my setup, the DK X48 was more stable but OC recovery is a pain on it. Ill have to decide which two of the three I want to keep.

[The Water Dog]

Im starting to like this board when i use my quad, get lots higher oc, 4 was stabil on Gigabyte P45 Extreme. But on this board i get 4,2 with less volts.
And the P45 mobo droops from 1,6 to almost 1,5....and Dfi X48 droops zero

[zsamz_]

Im starting to like this board when i use my quad, get lots higher oc, 4 was stabil on Gigabyte P45 Extreme. But on this board i get 4,2 with less volts.
And the P45 mobo droops from 1,6 to almost 1,5....and Dfi X48 droops zero

yes the best thing about this board it requires less volts for same overclock then any board i have used