**Official DFI LanParty UT X48-T2R(and LT) Discussion

[mikeyakame]

so basicly these are the settings (along with gtl) are what need's to be played with when shooting for high FSB on a quad?
Andrew

yep that sums it up mate

GTL References are used for common clock address strobe centre alignment, data strobe edge alignment, and determining logic high/low correctly so as to not read inverted data from logic low clock edge as non-inverted data from logic high clock edge so as to not invert 0 as 1 when 0 is 0 on logic high, or 1 as 1 when 1 is 0 on inverted logic low if differental clock voltage under or overshoots back inside overdrive region.

Where as MCH Vref references are external to AGTL+ bus, and are for FSB AGTL+ differential clock slew rate matching to Host BCLK slew rate, so that during MCH/DRAM cross clocking (read delay) DRAM DDR delay locked loop skews (from FSB AGTL+ clock on NB) and DRAM DQS (data strobe) can be phase aligned to FSB AGTL+ clock by means of Host BCLK clock gen reference which is same clock reference FSB is driven to.

Vref1-3 give additional offset compensation against Host BCLK reference for FSB clock, to shift voltage crossing point Vref3 higher or lower, and add offsets to Vref1 and Vref2 to correctly calculate Vref3,

If Vref1 at Vref+200mV is used when slew rate at receiver is too slow and voltage crossing couldnt be accurately determined to increase slew rate speed by extrapolating back to Vref3.

If Vref2 at Vref-200mV (previous Vref point) is used to calculate voltage crossing point Vref3 after the voltage has crossed Vref +- 200mv, and it undershoots or overshoots back within the overdrive region, new Vref3 is calculated to extrapolate correct slew rate leaving the overdrive region.

As you offset Vref3, apply same to Vref1 and Vref2 to make sure that in all scenarios Vref3 voltage crossing point reference calculation comes back the same offset you set at Vref3, so that FSB clock slew rate is matched to Host BCLK reference, and that it also matches slew rate of DRAM clock, CPU clock, PCIE clock, etc for common clock address strobes.

These help break an FSB wall because the wall exists when the circuit design can no longer stay within minimum requirements for FSB clock period stability and validity.