Quote Originally Posted by mikeyakame View Post
That makes a lot of sense Wiz!

Something along those lines would be executed by controlling say 3 or 4 dedicated GPIO pins which would be used to assert/deassert the VID pins based on the required voltage table bit mask to obtain 3 or 4 preset Performance Level VIDs? Ie. use different open GPIO pin combination to get 4 bit mask range, 00 01 10 11 of which each has a preset VID entry to connect VID0-VID7 pins based on what Voltage Table mask is needed to output each performance level voltage.

I'm not all that knowledgable on the GPIO functionality so I've just taken a stab at how i think it may be done, feel free to correct me if i've missed the target heh.
Correct. But normally amount of such GPIO controlable pins is reduced to required minimum during the PCB design (the rest VRM's VID pins are hardwired), so normally there is just 1 GPIO pin connected to VRM if 2 different voltages are needed, 2 pins if up to 4 voltages are needed etc. So maximum you can expect is having limited set of fixed voltages. And the maximum one is normally aready in use.