X48 Rampage Formula Preview.

[mikeyakame]

Well I confirm the clock skews are working I can even post at 400mhz FSB now! LOL It doesn't fix a broken cpu socket though but it seems they definitely help

At 400mhz fsb I'm using:

CPU Clk Skew = -100PS
NB Clk Skew = Normal

How did I know that seems right? Well Normal/Normal gives a longer delay on LCD Poster between CHECK CPU and VGA BIOS, 100/Normal gives a near instant response between the two

Seems skewing isn't too bad at this point.

Zucker,

You are going to have to be the GOD who breaks the magical 500mhz FSB mark, I'm having enough trouble right now breaking 400mhz

Edit:
PS C:\Users\mikey\linpack> .\linpack_xeon64.exe .\lp64.in
User Specified Datafile

Current date/time: Thu Feb 05 09:39:46 2009

CPU frequency: 3.600 GHz
Number of CPUs: 4
Number of threads: 4

Parameters are set to:

Number of tests : 2
Number of equations to solve (problem size) : 2000 14000
Leading dimension of array : 2008 14008
Number of trials to run : 6 4
Data alignment value (in Kbytes) : 4 4

Maximum memory requested that can be used = 1569180256, at the size = 14000

============= Timing linear equation system solver =================

Size LDA Align. Time(s) GFlops Residual Residual(norm)
2000 2008 4 0.189 28.3305 4.657913e-012 4.051814e-002
2000 2008 4 0.168 31.7649 4.657913e-012 4.051814e-002
2000 2008 4 0.165 32.2756 4.657913e-012 4.051814e-002
2000 2008 4 0.168 31.7843 4.657913e-012 4.051814e-002
2000 2008 4 0.161 33.1090 4.657913e-012 4.051814e-002
2000 2008 4 0.170 31.3822 4.657913e-012 4.051814e-002
14000 14008 4 44.732 40.9045 1.832709e-010 3.309677e-002
14000 14008 4 45.606 40.1207 1.832709e-010 3.309677e-002
14000 14008 4 43.486 42.0760 1.832709e-010 3.309677e-002
14000 14008 4 43.799 41.7756 1.832709e-010 3.309677e-002

Performance Summary (GFlops)

Size LDA Align. Average Maximal
2000 2008 4 31.4411 33.1090
14000 14008 4 41.2192 42.0760

End of tests

Poifect Couldn't even get this broken thing stable with GTLs, now its not throwing Linpack errors anymore above 333mhz FSB! With GTLs at 0.67x CPU and 0.63x NB.
Perhaps we can live without individual landing pin GTL adjustment after all Clock skews make a hell of a lot more difference for the reason I explained in the GTL thread.

GTLs alone only dynamically shift the problems of clock jitter but don't fix it, Clock Skews completely solve it