Quote Originally Posted by roller11 View Post
The setting of BCLK is an implementation detail and therefore is of no importance, all that matters is CPU clock.
Except that now we have an IMC and unfortunately quality differences there (and physical module configuration differences) at high memory/interface speeds are going to have wildly varying results as to what is stable at any setting and how much vCore and VTT required to be stable at specific settings.

Also there are performance gains to be had by increasing the Uncore clock to keep up with the core clock speed as you raise it. My point is we need to keep track of both Core and IMC quality across batches.

Also, you reminded me of another good point. It may be interesting to see if some chips can drop more voltage than others when disabling hyperthreading. I can drop much more voltage by disabling HT at high clock speeds than slow clock speeds and that's probably the norm but I'm not sure. You can significantly increase the max stable OC you can get by disabling HT and see no performance hit whatsoever for the software you are running if it doesn't use more than 4 threads.