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Thread: AMD Shanghai/Deneb Review Thread

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  1. #1
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    As soon as Ramm or anyone else gets his chip,we'll know how it OCs on air and performs .Some amount of chips will be available before the official launch.
    As for hiding comment,they are not hiding anything,but like Jazzman said,they are keeping the folks interested by leaking bit by bit during longer period of time.It would wear off if they had shown it all 1 month prior to release. As all can see from Chicago event,the chips are very tolerant to volts and run cool.2 or 3 more events like this one are scheduled until the launch so it will be interesting to see what others will say.

  2. #2
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    Quote Originally Posted by informal View Post
    As soon as Ramm or anyone else gets his chip,we'll know how it OCs on air and performs .Some amount of chips will be available before the official launch.
    As for hiding comment,they are not hiding anything,but like Jazzman said,they are keeping the folks interested by leaking bit by bit during longer period of time.It would wear off if they had shown it all 1 month prior to release. As all can see from Chicago event,the chips are very tolerant to volts and run cool.2 or 3 more events like this one are scheduled until the launch so it will be interesting to see what others will say.
    Sure but integrated memory controllers are easy to burn up and are NOT as tolerent of voltage. Ask Ramm about the last one he burnt up? That's something AMD and Intel will have to worry about.
    Quote Originally Posted by Movieman
    With the two approaches to "how" to design a processor WE are the lucky ones as we get to choose what is important to us as individuals.
    For that we should thank BOTH (AMD and Intel) companies!


    Posted by duploxxx
    I am sure JF is relaxed and smiling these days with there intended launch schedule. SNB Xeon servers on the other hand....
    Posted by gallag
    there yo go bringing intel into a amd thread again lol, if that was someone droping a dig at amd you would be crying like a girl.
    qft!

  3. #3
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    Quote Originally Posted by Donnie27 View Post
    Sure but integrated memory controllers are easy to burn up and are NOT as tolerent of voltage. Ask Ramm about the last one he burnt up? That's something AMD and Intel will have to worry about.
    That's why NB/L3 runs on separate power plane??
    You don't need crazy Vdimm volts in order to OC PhII.You have memory dividers and you use multies to OC the CPU,so the ram stays at the same clock all the time.I thought you knew this already ?
    All we know is that PhII ran at 1.9V .That's 1.9V for vcore.Uncore part(NB/L3) ran at much lower volts and clocks using constant NB multi and HTT of 200Mhz.

  4. #4
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    Quote Originally Posted by informal View Post
    That's why NB/L3 runs on separate power plane??
    You don't need crazy Vdimm volts in order to OC PhII.You have memory dividers and you use multies to OC the CPU,so the ram stays at the same clock all the time.I thought you knew this already ?
    All we know is that PhII ran at 1.9V .That's 1.9V for vcore.Uncore part(NB/L3) ran at much lower volts and clocks using constant NB multi and HTT of 200Mhz.
    I know about Phenom II, my comments were about folks being them up on Phenom 1 ANd that they WOULDN'T have to resort to such stuff. If you don't know what I'm talking about, ask Rammsteiner? 1.9v is a lot no matter what processor it's used on IMHO. Short term is one thing, think folks will be able to use 1.9v without LN, I don't think so. Yes, I know what an Un-Core is and even Intel is using that term now as well
    Last edited by Donnie27; 12-11-2008 at 09:14 AM.
    Quote Originally Posted by Movieman
    With the two approaches to "how" to design a processor WE are the lucky ones as we get to choose what is important to us as individuals.
    For that we should thank BOTH (AMD and Intel) companies!


    Posted by duploxxx
    I am sure JF is relaxed and smiling these days with there intended launch schedule. SNB Xeon servers on the other hand....
    Posted by gallag
    there yo go bringing intel into a amd thread again lol, if that was someone droping a dig at amd you would be crying like a girl.
    qft!

  5. #5
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    cute cat but letting it get so close to your new toy, Id feel really nervous and definattelly shoo it away from it.

    informal 16v is a little much lol
    Last edited by Caveman787; 12-11-2008 at 09:33 AM.

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    Quote Originally Posted by Macadamia View Post
    I don't think idle will win i7 though. They have per-core power gating. D:

    Normal 10-25% usage however... should be different.
    But i7 needs more juice on the uncore region than phenom on the nb section so I expect a lower consumption even in idle for denebs.
    Quote Originally Posted by iocedmyself View Post
    C&Q on the 45nm chips is really much improved, but full features aren't enabled yet, you'll actually be able to specify clock speeds you want to scale down to on the AM3 boards. As well as specify individual clock and power per/core i believe. I'm not sure if i can specify just how low the voltage and TDP has been tested at, but it really does put I7 to shame, for example have 1.0 Vcore @ 2.8 rock solid stable
    Griffin allows individual frequencies and voltages per core but the platform comes with three power planes there.
    Defining the lowest possible p-state is also possible on K10 platforms but it did not make sense with just two p-states.
    Quote Originally Posted by iocedmyself View Post
    Just wanted to give update i'm going to reinstall sandra and test interconct bandwidth and cache speeds now. So again any advice suggestions or even requests lemme know
    Thanks would be nice. Estimations based on early shanghai results showed big improvements on the intercore stuff. Would be interesting if it's the same on denebs.

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