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Thread: [Intel] There is NO TLB bug in Nehalem.

  1. #51
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    Quote Originally Posted by Oliverda View Post
    There are TLB bugs in Nehalem:

    AAJ42 X Plan Fix: Incorrect TLB Translation May Occur After Exit From C6

    AAJ59 X Plan Fix: Writes to IA32_CR_PAT or IA32_EFER MSR May Cause an Incorrect ITLB Translation


    AAJ54 X No Fix: Core C6 May Clear Previously Logged TLB Errors

    source: 10-12 pages
    That was already covered by Intel's response. See first post.

  2. #52
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    Exclamation

    Quote Originally Posted by soundood View Post
    it seems the irony of my post was lost in your non humour day, lighten up dude
    Urmm... Sorry I do not call that humour in any sense... especially the line "all your family will die of smallpox", sounds more like cursing.

    EDIT: Telling people's family to go and die a slow and horrible death is NOT funny and its certainly NOT humour! You can compare this kind of statements with those of terrorists and extremist threats. Seriously!
    Last edited by Ghostbuster; 12-02-2008 at 11:10 AM.

  3. #53
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    Quote Originally Posted by kl0012 View Post
    That was already covered by Intel's response. See first post.
    Intel just talked about the AAJ1 erratum. These erratums are still exist. See the official Intel PDF.
    -

  4. #54
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    Quote Originally Posted by Oliverda View Post
    Intel just talked about the AAJ1 erratum. These erratums are still exist. See the official Intel PDF.
    Guess how many TLB "issus" are still on 65nm C2 or X2.
    Last edited by Hornet331; 12-02-2008 at 05:58 AM.

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    Quote Originally Posted by Oliverda View Post
    Intel just talked about the AAJ1 erratum. These erratums are still exist. See the official Intel PDF.
    No. They talked about clarification AAJ1. And then other erratas were mentioned.
    SPEC CLARIFICATION AAJ1 was initially added due to an issue on the Intel® Core 2 Duo processor which was previously corrected with a BIOS update; this issue does not impact the Nehalem Family of CPUs. There are errata on the Intel® Core i7 processor that relate to the TLB. These all relate to improper translations or error reporting, and all of those that impact functionality have been fixed via BIOS updates prior to Core i7 launch.

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    Quote Originally Posted by Hornet331 View Post
    Guess how many TLB "issus" are still on 65nm C2 or X2.
    You can count: http://www.amd.com/us-en/assets/cont...docs/41322.pdf

    It has 42 erratums. The Shanghai/Deneb has less.

    So, the i7 has exactly 77 erratums. Ohh man...maybe that is the source of the brand i7.
    -

  7. #57
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    Quote Originally Posted by Oliverda View Post
    You can count: http://www.amd.com/us-en/assets/cont...docs/41322.pdf

    It has 42 erratums. The Shanghai/Deneb has less.

    So, the i7 has exactly 77 erratums. Ohh man...maybe that is the source of the brand i7.
    reading comprehension dude... i said TLB isuss, not erratas, also Core 2 Duo and Athlon X2.

  8. #58
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    Quote Originally Posted by Oliverda View Post
    You can count: http://www.amd.com/us-en/assets/cont...docs/41322.pdf

    It has 42 erratums. The Shanghai/Deneb has less.

    So, the i7 has exactly 77 erratums. Ohh man...maybe that is the source of the brand i7.
    Whoa, epic. Nice find
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    Quote Originally Posted by Oliverda View Post
    There are TLB bugs in Nehalem:

    AAJ42 X Plan Fix: Incorrect TLB Translation May Occur After Exit From C6

    AAJ59 X Plan Fix: Writes to IA32_CR_PAT or IA32_EFER MSR May Cause an Incorrect ITLB Translation


    AAJ54 X No Fix: Core C6 May Clear Previously Logged TLB Errors

    source: 10-12 pages
    Good find!!! If I was you I would send every errata on Ci7 I find to FUDZILLA so that he can make an article on it We have to find something wrong with that pesky Ci7 before it makes it to servers.

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    Quote Originally Posted by Oliverda View Post
    You can count: http://www.amd.com/us-en/assets/cont...docs/41322.pdf

    It has 42 erratums. The Shanghai/Deneb has less.

    So, the i7 has exactly 77 erratums. Ohh man...maybe that is the source of the brand i7.
    There may be missing errata numbers. Errata that have been resolved from early revisions of
    the processor have been deleted, and errata that have been reconsidered may have been
    deleted or renumbered.
    Its not entirely the same. Plus nor Intel or AMD actually list all erratas. They list what is "needed".
    Crunching for Comrades and the Common good of the People.

  11. #61
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    Quote Originally Posted by Oliverda View Post
    It has 42 erratums. The Shanghai/Deneb has less.
    How do you know that? Specification update for Shanghai wasn't released yet.

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    I don't get it. The Intel guy says "there is no TLB bug" and then explicitly describes an issue where corruption occurs and states that it was fixed with a BIOS update prior to launch.

    ...so you're saying there's a TLB bug, but it's alright since you patched it with software? That sounds familiar.
    Particle's First Rule of Online Technical Discussion:
    As a thread about any computer related subject has its length approach infinity, the likelihood and inevitability of a poorly constructed AMD vs. Intel fight also exponentially increases.

    Rule 1A:
    Likewise, the frequency of a car pseudoanalogy to explain a technical concept increases with thread length. This will make many people chuckle, as computer people are rarely knowledgeable about vehicular mechanics.

    Rule 2:
    When confronted with a post that is contrary to what a poster likes, believes, or most often wants to be correct, the poster will pick out only minor details that are largely irrelevant in an attempt to shut out the conflicting idea. The core of the post will be left alone since it isn't easy to contradict what the person is actually saying.

    Rule 2A:
    When a poster cannot properly refute a post they do not like (as described above), the poster will most likely invent fictitious counter-points and/or begin to attack the other's credibility in feeble ways that are dramatic but irrelevant. Do not underestimate this tactic, as in the online world this will sway many observers. Do not forget: Correctness is decided only by what is said last, the most loudly, or with greatest repetition.

    Rule 3:
    When it comes to computer news, 70% of Internet rumors are outright fabricated, 20% are inaccurate enough to simply be discarded, and about 10% are based in reality. Grains of salt--become familiar with them.

    Remember: When debating online, everyone else is ALWAYS wrong if they do not agree with you!

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  13. #63
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    Quote Originally Posted by kl0012 View Post
    How do you know that? Specification update for Shanghai wasn't released yet.
    guess we have a new magic crystal ball user.

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    Quote Originally Posted by kl0012 View Post
    How do you know that? Specification update for Shanghai wasn't released yet.
    Well simple AMD=good, Intel=bad. Silly wabbit

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    Quote Originally Posted by Oliverda View Post
    There are TLB bugs in Nehalem:

    AAJ42 X Plan Fix: Incorrect TLB Translation May Occur After Exit From C6

    AAJ59 X Plan Fix: Writes to IA32_CR_PAT or IA32_EFER MSR May Cause an Incorrect ITLB Translation


    AAJ54 X No Fix: Core C6 May Clear Previously Logged TLB Errors

    source: 10-12 pages
    Just as a note: C6 state means the system is in very deep sleep. PLLs, caches etc is turned of. And system state is in main memory only.

    I would claim this is a non issue until i7 laptops are released.

    Last edited by Shintai; 12-02-2008 at 06:24 AM.
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    Quote Originally Posted by naokaji View Post
    Well, they contradict themself so often that atleast one of the 100K 2 line stories has to be true
    Best line in the thread! Unfortunately I disagree. IMHO, I think FUD knows exactly what he's doing. I call it "Hit Phishing" or "Hit Mining". He knows sensationalism and outrageous-ness gets hits. Hits brings in the Bucks. Sure, there's enough folks hoping, wishing and praying Intel slips up to give more hits. Then there are the folks going there to argue the other side and so on. But shame on anyone calling themselves a n Xtreme-Systems Geek or Enthusiast even clicking on that site (or the other) more than once a week and then only for laughs. Folks flocking there for either Pro or Con only encourages him to continue to post such crap-tacular BS!
    Quote Originally Posted by Movieman
    With the two approaches to "how" to design a processor WE are the lucky ones as we get to choose what is important to us as individuals.
    For that we should thank BOTH (AMD and Intel) companies!


    Posted by duploxxx
    I am sure JF is relaxed and smiling these days with there intended launch schedule. SNB Xeon servers on the other hand....
    Posted by gallag
    there yo go bringing intel into a amd thread again lol, if that was someone droping a dig at amd you would be crying like a girl.
    qft!

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    Quote Originally Posted by Shintai View Post
    Just as a note: C6 state means the system is sleeping. PLLs, caches etc is turned of. And system state is in main memory only.

    I know, but for example the AAJ59 is not a C6 state related erratum.

    Quote Originally Posted by kl0012 View Post
    How do you know that? Specification update for Shanghai wasn't released yet.
    You'll see it.
    -

  18. #68
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    Quote Originally Posted by Particle View Post
    I don't get it. The Intel guy says "there is no TLB bug" and then explicitly describes an issue where corruption occurs and states that it was fixed with a BIOS update prior to launch.

    ...so you're saying there's a TLB bug, but it's alright since you patched it with software? That sounds familiar.
    The issue is people use overall macro generalizations for terms they dont understand. So anything with bug and TLB must mean the same as AMDs TLB bug. Tho they may not have a single bit in common besides regarding to the TLB.
    Crunching for Comrades and the Common good of the People.

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    Quote Originally Posted by Oliverda View Post
    You can count: http://www.amd.com/us-en/assets/cont...docs/41322.pdf

    It has 42 erratums. The Shanghai/Deneb has less.

    So, the i7 has exactly 77 erratums. Ohh man...maybe that is the source of the brand i7.
    This will slowly degrade into another flame war... AMD has not published errata for Shanhai/Deneb, Barcleona had at one point over 300 errata ... the number of errata does not make or break a product. AMD removes errata entry if there is no issue or the internalize it ... the index them sequentially, the last errata entry is number 355 ... hence, a total of 355 errata were discovered since the first stepping.

    These type of problems are discovered after validation, which is pretty extensive from the commentary Torvals suggests. This is just a bunch of hay over nothing.
    Last edited by JumpingJack; 12-02-2008 at 06:48 AM.
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    Quote Originally Posted by qurious63ss View Post
    Well simple AMD=good, Intel=bad. Silly wabbit
    QFT!
    Quote Originally Posted by Movieman
    With the two approaches to "how" to design a processor WE are the lucky ones as we get to choose what is important to us as individuals.
    For that we should thank BOTH (AMD and Intel) companies!


    Posted by duploxxx
    I am sure JF is relaxed and smiling these days with there intended launch schedule. SNB Xeon servers on the other hand....
    Posted by gallag
    there yo go bringing intel into a amd thread again lol, if that was someone droping a dig at amd you would be crying like a girl.
    qft!

  21. #71
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    Quote Originally Posted by Particle View Post
    I don't get it. The Intel guy says "there is no TLB bug" and then explicitly describes an issue where corruption occurs and states that it was fixed with a BIOS update prior to launch.

    ...so you're saying there's a TLB bug, but it's alright since you patched it with software? That sounds familiar.
    The point in question was a spec clarification, this is not a bug ... the errata list other bugs that are either benign or have been addressed with microcode updates. ... not terribly difficult to understand.
    One hundred years from now It won't matter
    What kind of car I drove What kind of house I lived in
    How much money I had in the bank Nor what my cloths looked like.... But The world may be a little better Because, I was important In the life of a child.
    -- from "Within My Power" by Forest Witcraft

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    Quote Originally Posted by Oliverda View Post
    You can count: http://www.amd.com/us-en/assets/cont...docs/41322.pdf

    It has 42 erratums. The Shanghai/Deneb has less.

    So, the i7 has exactly 77 erratums. Ohh man...maybe that is the source of the brand i7.
    Barcelona could of just had 1 errata, TLB bug, and C2 could of had 100s but still barcelona's was a show stopper and that's the difference. Point being that you can't just count errata and say this process/arch is better then the other one it just doesn't work that way.
    Last edited by qurious63ss; 12-02-2008 at 06:42 AM.

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    Quote Originally Posted by Shintai View Post
    The issue is people use overall macro generalizations for terms they dont understand. So anything with bug and TLB must mean the same as AMDs TLB bug. Tho they may not have a single bit in common besides regarding to the TLB.
    Well it's apparent they shared a major thing in common. Data corruption and system hangs.

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    Quote Originally Posted by freeloader View Post
    Well it's apparent they shared a major thing in common. Data corruption and system hangs.
    Yes seems that the barcelona and c2 TLB bug could of caused the same issues. Why it wasn't a big deal on C2 I really don't know maybe no one uses virtual on c2 but again they have not found a TLB bug on nehalem. As jack already mentions this is a spec clarification for something that was found on C2 and already fixed.

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    Quote Originally Posted by LOE View Post
    You mean you understand? Technically? Care to explain?
    Quote Originally Posted by JumpingJack View Post
    This will slowly degrade into another flame war...
    Wow, you have predicted the future, it's already happening. Please tell me should I buy AMD or Intel stock or Mcdonald's?

    qurious63ss, I don't think you understand the difference between "showstopper bug" and errata... if Intel's CPU are buggy people *will* notice and they *will* have to recall or replace their CPUs the way AMD did.
    Quote Originally Posted by freecableguy
    the idiots out number us 10,000:1

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