Quote Originally Posted by m^2 View Post
Well I posted in rush, I've been thinking not of "a TLB bug" but "the TLB bug".
It would be extremely unlikely that both companies made the same mistake. Especially that Intel knew of AMD's problem.

IMO the hype was caused by the way AMD handled the problem - they shipped flawed review samples to get better benchmark scores.
Huh ??

AMD's problem was huge compared to this nitpickin an errata list.AMD's problem was that K10 failed validation at major OEMs , that's HP,IBM,Fujitsu,etc.When that happens you're royally screwed.Those major OEMs didn't want to touch K10 with a 10 ft pole.
When you ship servers in mission critical areas ( industry, banking,etc ), a once in a while system crash ( which wasn't so rare in virtualized environments it seems, which btw is the current hottest trend ) is simply not acceptable.

Chips can have hundreds of errata , as long as they pass the most stringent validation requirements you're fine.
The difference is that with K10 people in the industry started whispering and gossip sites picked it up ; in this case a dude searched an errata list ( guess what genius, that's published after validation => wasn't considered a game stopper ) and sent a link a FUD.