The clk fine delay settings don't seem to be doing much for me; I've found I can't raise the delay over about 280ps or so when trying to run 434FSB and my Ballistix at 650MHz C5, 2.38V. If I do change it higher than that the board won't post, and even at 280ps with that VDIMM setting I get 6-7 digit errors in memtest #5![]()





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