Last edited by Pyr0; 11-25-2008 at 11:11 AM.
i950 (3035B684)
Gigabyte EX58A-UD3R
3x4GB G.Skill PC3-12800 7-8-7-24
HIS Radeon HD 6970 2GB & Dell 3007WFP-HC
Asus Xonar DX
128GB C300, Velociraptor & Sammy F3's
Corsair AX850W
Windows 7 Ultimate x64 SP1
nah dude that solved the hanging issue
now trying to solve the gtl issue
try linpack 50 run for 2x1gb and 15 runs for 4gb
u will get what i mean..
it was a issue that i had running 2x1gb at 2000mhz CL8
memtest HCI pass... Vcore and GTL confirmed..
bun linpack can even run 50 runs
but at the 13th run the results once in a while shows faults...
ure cpu skew/nb skew shows promise + the dram vtt ...
oh yeah even had some weird results with sb 1.1v
but that one still inconclusive..
again a crazy board..
Last edited by cstkl1; 11-25-2008 at 11:54 AM.
I've tested and thought some more on the 200 strap....
The main issue with tRD and cL combinations in certain FSB ranges, is non-allowable combinations for POST, resulting from MCH minimum timing limitations.
Earlier tests showed that the 200 strap allowed a lower tRD value to be used for a given CL etc, compared to what 266 and 333 straps would allow for POST.
eg: 200 strap allows POST/stability with CL7/tRD5, but 266 and 333 straps only allow minimum tRD6 with CL7.
Regardless of whether it works for DDR3, the existing (DDR2) tRD equation doesn't include a discrete reference to the Strap in use (other than including the divider in use). There would seem no allowance in the equation to predict the differences in POST behaviour, when using 1:2 divider on different straps.
Yet on this board there are differences in Strap/tRD POST allowability, which also seem independent of FSB (in 400-500FSB range I tested).
Despite the 200 strap allowing lower tRD values to POST, I would guess that the minimum allowable MCH timing (for POST) may not actually be lower on the 200 strap.
If lower allowable MCH latency resulted from using the 200 strap, then 200strap/CL8/tRD6 would be faster than 266 or 333 strap with CL8/tRD7.
Instead (I suspect), some other latency is introduced/forced by the 200 strap, which even with a lower tRD value, does not fall below the net minimum time for allowable POST.
If it's something along those lines, a forced increase in overall MCH latency (as suspected of the 200 strap) may allow POST/stability with lower tRD value (than 266 and 333 straps allow), but may not actually be better than neutral in terms of net MCH 'bandwidth' and/or stability, compared to other 'tighter' straps with higher minimum allowable tRD.
According to Everest, the 200 strap as tested gives lower performance, tRD for tRD, than 266 or 333 straps, with similar low performance apparent on the 400 strap too.
This doesn't mean that the 200 strap isn't worth using - it may be more stable - just that any expected benefit of allowing lower tRD values, may not come with it.
slowly piecing it together I hope, but just from incomplete information/knowledge
475x9 / 950 / 1:2 / CL8 / CT Strong / tRD6 / 200 strap
475x9 / 950 / 1:2 / CL8 / CT Strong / tRD7 / 200 strap
475x9 / 950 / 1:2 / CL8 / CT Strong / tRD7 / 266 strap
475x9 / 950 / 1:2 / CL8 / CT Strong / tRD7 / 333 strap
475x9 / 950 / 1:2 / CL8 / CT Strong / tRD7 / 400 strap
![]()
Maximus V GENE [0086] :: 3770K L212B244 :: H70 :: EB3103A (PSC)
CL|WCL|RTL performance (SB) : 32M scaling charts : PSC WCL > CL performance bug
All results with 475x9 / 950 / 1:2 / CL8
CT AUTO / tRD6 / 200 strap
CT Lighter / tRD6 / 200 strap
CT Light / tRD6 / 200 strap
CT MODERATE / tRD6 / 200 strap
CT STRONG / tRD6 / 200 strap
CT STRONGER / tRD6 / 200 strap
no result - POST ok but no Windows startup
CT LIGHTER / tRD7 / 200 strap
![]()
Maximus V GENE [0086] :: 3770K L212B244 :: H70 :: EB3103A (PSC)
CL|WCL|RTL performance (SB) : 32M scaling charts : PSC WCL > CL performance bug
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