X48 Rampage Formula Preview.

[mikeyakame]

Zucker2k,

When you've got some time would you be able to run a few scenarios for me with AI Clock Twister settings. It seems like they are giving me fixed values from what is probably a fixed table for each setting. DRAM Clock Skews need to be set to Normal on CHA/CHB and all CPL phase pull ins must be disabled. DRAM Static Read shouldn't affect the the results from what I can tell.

Values to go here.

AI Clock Twister
-Lighter -> -Stronger

Dimm1 Fine Clock Delay 5T
Dimm2 Fine Clock Delay 3T
Dimm3 Fine Clock Delay 5T
Dimm4 Fine Clock Delay 3T

Took a lot of samples at PL7/PL8 with all clock twister values and varying Phase pull-ins, and those values appear to be common.

I have a good 20 or so MCHBAR register dumps to analyze and compare for all the samples I took tonight, which will take me a good week to properly go over and over to isolate particular register values for each change from the changes to counter registers for things like Errors, Load Performance, Bus clock ticks, Transit delays, etc. Intel MCHBAR docs for all chipsets are sort of vague, and for the most part just outline the critical register values with regard to memory timings, memory segment addressing, memory performance counters, and so on.

There needs to be more people involved to give their values for certain FSBs. The xT or yT is because when I changed from 483MHz FSB to 485MHz FSB the values seemed to get more aggressive. I can't explain this.
It possibly changes some other hidden MCHBAR registers, but for time being until we can know their locations Dimm Clock Fine Delay seems to be the most useful across the board.

DRAM Clock Skew
50PS is equivalent to 1T which may be in UCLKs, differential clocks.

Advance 50PS = -1T
Delay 50PS = +1T

These can be checked with Everest Ultimate Edition under the Dimm1-4 Fine Clock Delay timings in Chipset. Normal is equivalent to the value set by the skew tables for the memory subsystem. This might vary between different Memory Dimm's. I only have 2 sets to test with unfortunately.


AI Clock Twister also effects AI Transaction Booster when set to Auto. More aggressive AI Clock Twister setting increases likelihood of Phase Pull-Ins for Common Performance level.

AI Trans Booster AUTO, 5:6 Divider with AI Clock Twister Stronger, CPL 10, Phase Pull-in PHA1
AI Trans Booster AUTO, 4:5 Divider with AI Clock Twister Stronger, CPL 9, Phase Pull-In PHA1, PHB1
AI Trans Booster AUTO, 3:4 Divider with AI Clock Twister Stronger, CPL 7, Phase Pull-in PHA1, PHA3, PHB1, PHB3
AI Trans Booster AUTO, 2:3 Divider with AI Clock Twister Stronger, CPL 6, Phase Pull-in PHA1, PHB1
AI Trans Booster AUTO, 1:1 Divider with AI Clock Twister Stronger, CPL 5, Phase Pull-in PHA1

Those are only scenarios I can recall. Its been a while but I am pretty sure thats the values the bios gives.

Phase pull-ins for Common Performance Level in AI Transaction Booster.

Number of phases is determined by combination of Internal Memory Divider and Bus BCLK Scalable frequency.
4:5 divider has 4 phases on each memory channel, and 5 phases on mch.
10:12 divider aka 5:6 has 5 phases on each memory channel and 6 phases on mch.

Order of pulling in phases:
First Phase
Second Last Phase (or last depending on phase count, for > 4 phases use second last)
Last Phase
Second Phase
Middle Phase (if using 10:12 divider)

Channel A Phases are the most aggresive, by incrementing Read Delay Phase Adjust Tck value.
This value in Everest relates to tRD transaction BUS_DRDY assert skew. Neutral/0T is Intel spec max turnaround for data to be ready on the bus for given Performance Level. This is the delay skew between DRAM burst read command assert until the MCH can issue BUS_DRDY assert and burst data transmission across the bus to destination.

The advance in skew for a given phase, is set by the number of phases. As more phases are added, each additional phase incurs a penalty of [ 2 ^ nPhase - 1 ]T clocks turnaround for transactions.

Phase 1 = tRD skew advance +1T [ 2 ^ 1 - 1 ]
Phase 2 = tRD skew advance +2T [ 2 ^ 2 - 1 ]
Phase 3 = tRD skew advance +4T [ 2 ^ 3 - 1 ]
Phase 4 = tRD skew advance +8T [ 2 ^ 4 - 1 ]
Phase 5 = tRD skew advance +16T [ 2 ^ 5 - 1 ]


Total Read Delay Phase Adjust clocks
Channel B Phases are the least aggressive, by generally only incrementing Dimm Fine Clock Delay clocks. 1T increases are the norm, and not on all phases. 1T = 50ps DRAM clock skew delay.