How to set up GTL Ref Values for 45nm & 65nm

[mikeyakame]

Hi, does anyone know if clock skews have an effect on GTL settings ?

I have just updated my bios and had to change from -'ve to +'ve GTL settings after setting :-
CPU Clock Skew: Delay 300ps
NB Clock Skew: Delay 200ps

Maybe Asus just programmed the bios wrong ???.

hmm its possible I suppose, since gtl reference determines clock period, skewing it probably changes the clock assert/deassert timing in relation to the base clock and gtl reference voltage is used to determine a valid low or high clock with respect to the clocking source (bclk). It may be skewing the clock assert/deassert for either the cpu or nb could create a situation where either assert/deassert for nb/cpu clock happen too early or too late and occur inside the crossing threshold or basically not within the valid area of a clock period, which exists where the high clock crosses the crossing threshold on the rising edge and crosses it again on the falling edge (determined by slew rate, rising of voltage / distance unit), and on the low clock it happens the other way around.


nb clock skew and cpu clock skew work a little different than the name suggests. nb clock skew actually refers to mch side of nb with relation to the fsb base clock, and cpu clock skew is the cpu clock in relation to the fsb bclk. dram clock skew is actually the skewing of the address strobe clock between the dram controller side of mch and actual memory modules.