Deneb Samples are almost out

[topdog]

It's getting closer,seems it will be Q4 2008

Source

AMD is doing the final touch to its quad-cores and from what we’ve heard, the new 45nm quad-core should overclock much better than the previous one. You can definitely expect that the normal 45nm sample should work over 3GHz, but we learned to be cautious about AMD’s promises as this company definitely taught us that we should see it to believe it.

The chips will debut either in very late November or early December and we would bet on late December. It looks that chips will be widely available in December, while samples should be out in November.

[Hornet331]

uhn i stoped reading after "we learned"... mark fud news as fud....

[informal]

They better be out if AMD intends to launch them in Q4.. What i want to say it's common logic the samples are out.It's like saying :"Gee,it's 5 30 in the morning ,the sun will rise soon".

[Ghigo]

AMD looks like want fight for christmas sells :

.
Phenom X4 20550 Deneb 4x 3,0 GHz 6 MiB AM2+ 125 W launch Nov.08
Phenom X4 20350 Deneb 4x 2,8 GHz 6 MiB AM2+ 125 W launch Nov.08


http://www.hardware-infos.com/news.php?news=2492

[naokaji]

Launch is one thing, actual retail avalaibilty another.

Anyway, it would be good for Amd if they could indeed manage to get them in the shops this year.

[Hornet331]

I really hope they are out soon, so all this "20-25% more performance/clock (then agena) -> faster then yorkfield" BS ends, and we see real numbers.

[informal]

I really hope they are out soon, so all this "20-25% more performance/clock (then agena) -> faster then yorkfield" BS ends, and we see real numbers.

20-25% over Agena is really a stretch.On the other hand,a good 10-15% is not impossible and if they managed that,a 3-3.2Ghz Deneb within 125W in AM3 package is not unreasonable in Q1.Those chips will be a lot faster than 2.6Ghz Agena we have now and if they clock well(3.6-4Ghz,air, on SB750),AMD may again be very competitive in the mid range.

[Bellisimo]

20-25% over Agena is really a stretch.On the other hand,a good 10-15% is not impossible and if they managed that,a 3-3.2Ghz Deneb within 125W in AM3 package is not unreasonable in Q1.Those chips will be a lot faster than 2.6Ghz Agena we have now and if they clock well(3.6-4Ghz,air, on SB750),AMD may again be very competitive in the mid range.

qft

[Flambo]

Unfortunately for AMD, Nehalem just launched and seem to be kicking serious behind. Deneb might just allow AMD to catch up with Penyrn if they are lucky. It looks like Intel took AMD's Barcelona architecture and perfected it. Still, it would be nice to have Deneb out as it might offer an low cost alternative. Can AMD create something like hyperthreading? I know Cinebench isn't really used for anything useful but come on... don't let Intel cream you so bad! Come on Deneb, I want that 20-25 % increase in performance!!

[Sentential]

If its a straight optical shrink (its not but just for the sake of this arguement) you're going to shrink it down by about 30%.

Assuming that the die shrink causes the chip to clock on a percentage basis with a conservative clock of 3200 (which most do with ACC) We are looking at Deneb clock speeds of around 4200 - 3900 mhz overclocks (which is quite close to what we saw with early screenshot leaks.

Part of why I went with Deneb is the assumption that the i7s when they go retail will be highly limited by what they can clock to (similar to the Q9300 on a X38 or an X48 based chipset)

That being said a 3.5ghz i7 will get romped by a 4ghz Deneb IF the price is the same, all bets are off however if the i920 does 4ghz @ release on retail chips

[Hornet331]

For SMT they would need to redesign the Chip, maybe with K11 but thats far way.

[informal]

Digitimes news are interesting,hinting at Nov as release date:
http://www.digitimes.com/news/a20081104PD203.html

More details of AMD 45nm CPU lineup revealed

Latest news
Monica Chen, Taipei; Joseph Tsai, DIGITIMES [Tuesday 4 November 2008]

AMD is planning to launch two 45nm quad-core desktop CPUs (Deneb) – the Phenom X4 20550 and 20350 for socket AM2+ systems with core frequencies of 3GHz and 2.8GHz, respectively in November this year, according to sources at motherboard makers.

Hardware-info hints at 8 November as a release (graph says launch) date:
. Codename Takt L3-Cache Sockel TDP Launch
Phenom X4 20550 Deneb 4x 3,0 GHz 6 MiB AM2+ 125 W Nov.08
Phenom X4 20350 Deneb 4x 2,8 GHz 6 MiB AM2+ 125 W Nov.08

[leoy]

NOv 8?
Propably false....
Although could be great.

[demonkevy666]

If its a straight optical shrink (its not but just for the sake of this arguement) you're going to shrink it down by about 30%.

Assuming that the die shrink causes the chip to clock on a percentage basis with a conservative clock of 3200 (which most do with ACC) We are looking at Deneb clock speeds of around 4200 - 3900 mhz overclocks (which is quite close to what we saw with early screenshot leaks.

Part of why I went with Deneb is the assumption that the i7s when they go retail will be highly limited by what they can clock to (similar to the Q9300 on a X38 or an X48 based chipset)

That being said a 3.5ghz i7 will get romped by a 4ghz Deneb IF the price is the same, all bets are off however if the i920 does 4ghz @ release on retail chips

http://www.bmighty.com/blog/main/arc...tting_out.html

die shrink + removed resistor on parts of the Cache. lower heat lower load.

4Mb (Barcelona/Agena)vs 8Mb (Shanghai/Deneb) on average core 2 duo was a 10% increase with 2mb vs 4mb.

now shanghai/deneb brings 15% more IPC the Agena.

HT3.1 really helps the L3 cache which needs to be closer to core speeds.

[Bellisimo]

4Mb (Barcelona/Agena)vs 8Mb (Shanghai/Deneb) on average core 2 duo was a 10% increase with 2mb vs 4mb.

imo, this is because the IMC was on the NB, L2 caches helps to hide the memory latency (L3 in nehalem and K10/K10.5)

but i really like to think about deneb as a RV770, which means a RV670 done right
i dont expect it to beat nehalem, but if it is a K10 done right, it may end op close in some scenarios

at least deneb will offer full control over the cpu, unlike nehalem where only the extreme part is usefull for overclocking and high mem speeds

[Jacky]

http://www.bmighty.com/blog/main/arc...tting_out.html

die shrink + removed resistor on parts of the Cache. lower heat lower load.

4Mb (Barcelona/Agena)vs 8Mb (Shanghai/Deneb) on average core 2 duo was a 10% increase with 2mb vs 4mb.

now shanghai/deneb brings 15% more IPC the Agena.

HT3.1 really helps the L3 cache which needs to be closer to core speeds.

Geez. There is not HT3, it won't be 15% (at least that's my educated guess) faster, samples have been out for months* and now launch those suckers AMD!
* as always sensationalist wording by FUD. It should say something like "samples of the finalized steppings/hardware".

OBR, thank you for teasing us - like always - that's why we love you, don't we? Maybe for once you will answer our questions or SU: what do you mean? not that high clocked? not launching this year?

[ownage]

I hope so.
Look at what Charlie Demerjian has to say:

http://www.realworldtech.com/forums/...94137&roomid=2

Just wait, they are going to strike back hard in a year, they have a MUCH bigger socket coming. Intel has _NO_ response to AMD's socket size war, none at all.

-Charlie

[demonkevy666]

imo, this is because the IMC was on the NB, L2 caches helps to hide the memory latency (L3 in nehalem and K10/K10.5)

but i really like to think about deneb as a RV770, which means a RV670 done right
i dont expect it to beat nehalem, but if it is a K10 done right, it may end op close in some scenarios

at least deneb will offer full control over the cpu, unlike nehalem where only the extreme part is usefull for overclocking and high mem speeds

l3 cache is faster then main memory

main 63ns vs L3 7ns

AMD 790FX Chipset AMD 790FX Chipset is designed to support up to 5200MT/s HyperTransport 3.0 (HT 3.0)

HT 3.0 is 2600mhz

[informal]

I think OBR was speaking about samples being out(as in "leaky" hands of testers).

Back to INQ again,Charlie just wrote about the leaked Shanghai memo here.Take it with a grain of salt.It's still an interesting piece ,especially the bold part(no idea if it is a word from testers or how reliable it is).

AMD Shanghai memo leaks

Slightly juicy cheerleading

By Charlie Demerjian: Tuesday, 04 November 2008, 7:54 AM

AN AMD MEMO from Randy Allen, Senior Vice President, Computing Solutions about Shanghai has leaked out to the Polish site PC Lab. It paints a rosy picture of Shanghai for the launch to an internal audience.

There are a few key points to note, bearing in mind that it is written from a rather biased viewpoint. First is that AMD is shipping Shanghai chips to customers now, not a big shock considering it launches in less than two weeks. If they weren't shipping by now, then AMD would have some rather serious logistics to work out in the next 14 days or so.

Then comes the interesting point that AMD has a time to market advantage over 'our competitor', which is true since 2S Nehalems won't ship for about three more months, and then it will take a bit to ramp from there. Early word is that Shanghai will beat Penryn on clock-for-clock performance, the real question is whether or not they can jack the speed up.

Mr Allen then goes on to say that Shanghai shipped about 1Q early, and to make matters more hopeful, it is supposedly shipping under planned TDP and higher than expected clocks. Both of these are credited to getting the engineering back on track, and the new 45nm immersion process. Lets hope for the industry that this is a systemic change, not a fluke.

From there, the memo goes on to talk about price/performance, and price/performance-per-watt leadership. I take this as a bit telling that they won't have the outright performance lead, likely due to Intel's clock advantage, but it isn't a bad place to be considering how 2008 has been for the company up until this point.

Virtualisation is also leaned upon heavily, and it has been one of AMD's strong points up until now. With Nehalem pulling the memory controller on die, it will remain to be seen how much of that advantage goes away, virtualising this has been the killer app for AMD over the last few years.

In the end, it is clear that AMD thinks it has a winner on its hands. It will be quite interesting to see how Shanghai stacks up, both later this month vs Penryn, and in early 2009 vs Nehalem.

Game on once again. µ

[savantu]

I think OBR was speaking about samples being out(as in "leaky" hands of testers).

Back to INQ again,Charlie just wrote about the leaked Shanghai memo here.Take it with a grain of salt.It's still an interesting piece ,especially the bold part(no idea if it is a word from testers or how reliable it is).

It's said by AMD , do bother to read more closely the article.And it talks seemingly about 2S.I wouldn't be surprised to see higher clocked Shanghais beating Harpertown in enough tasks at 2S.

However , Nehalem 2S is an altogether different pie.

[Bellisimo]

l3 cache is faster then main memory

i dont state otherwise, i just was trying to say the L3 cache on nehalem/K10/K10.5 hides the memory latency instead of their L2 cache
L2 cache is used to hide memory latency on Core/Core2 and every other cpu which hasnt an IMC on die

[Hornet331]

l3 cache is faster then main memory

main 63ns vs L3 7ns

AMD 790FX Chipset AMD 790FX Chipset is designed to support up to 5200MT/s HyperTransport 3.0 (HT 3.0)

HT 3.0 is 2600mhz

thats not the real latency of the 3rd lvl cache, its hidden by the prefetchers, its somewhere ~30-40ns same goes for nehalem.

[Calmatory]

Cache increases and comparison against Core architecture are more than useless really. Why? Because another architecture has IMC and another one does not. Besides, cache misses are unique to both architectures and increasing cache size to compensate and reduce the miss is different for both architectures. Yes, some guesstimations can be made, but they shouldn't be considered very valid unless otherwise proven in practice.

It also depends what kind of cache misses they are. E.g. instruction cache miss is more vital than data cache miss.

[informal]

It's said by AMD , do bother to read more closely the article.And it talks seemingly about 2S.I wouldn't be surprised to see higher clocked Shanghais beating Harpertown in enough tasks at 2S.

However , Nehalem 2S is an altogether different pie.

Exactly where in the memo is Penryn per clock comparison mentioned?Where does Charlie speak of the source of the clock per clock superiority of Shanghai?

It only says "Early word is...".It could be from AMD of course,but C0 ES are out since April,that was 7 months ago.

[demonkevy666]

Cache increases and comparison against Core architecture are more than useless really. Why? Because another architecture has IMC and another one does not. Besides, cache misses are unique to both architectures and increasing cache size to compensate and reduce the miss is different for both architectures. Yes, some guesstimations can be made, but they shouldn't be considered very valid unless otherwise proven in practice.

It also depends what kind of cache misses they are. E.g. instruction cache miss is more vital than data cache miss.

L3 cache went form 32 way to 48 way.

been on every CPU-Z I've seen.