Real Temp - New temp program for Intel Core processors

[rge]

It's me again with yet another insane idea.
First of all : rge, you rock!
Now back to the idea. As we know Intel might mean different things with their new Target TJ value. It seems obvious that those 70C & 80C for 65nm mean something different than 95-100C for 45nm despite being given the same name. But, as rge has proved, at DTS=0 we are supposed to get IHS temps very close or equal to those listed in thermal specification (72-74C for 45nm CPUs). But personally I cannot believe in a gradient of 27C (or maybe even more, as it will most likely increase with higher temps) between core temps and IHS. The previous P4 testing is a good proof to that. On a 65nm CPU this gradient would've been much lesser and much more reasonable, should we decide to use Intel's TJ Target value of 70C for B2 or 80C for G0 (15-20C offset from guessed TJmax used earlier) and IHS values taken from processorfinder of 60.1C and 72C respectively. So maybe these new "official" numbers for 65nm aren't that wrong? Thermal specification for 45nm is very close to that of 65nm G0 stepping (72-74 vs 72). If we (hypothetically) assume TJmax=80C (same 20C offset) for 45nm CPUs then we'd see only 7C gradient in rge's testing and 6-8C gradient at DTS=0 according to Intel's specs (72-74 IHS temps and this hypothetical 80C Tjmax). The abnormally low core temperatures in this case at idle & medium load could be explained by sensors' inaccuracy (slope error) while high load core temps would be more accurate & close to IHS temps.

Sorry for my English, I'm not sure I expressed everything the way I meant to.

I am now positive there is a 27C gradient from tcasemax to tjmax at full load (high TDP), measuring at true IHS versus core. Note this has nothing to do with the small few C gradient from DTS die temps to cpu diode (between cores still in die with very high thermal conductance). But to see this gradient from IHS to core temps you have to be at full load (high TDP) with a heatsink. A large gradient was duplicated at university testing better than mine on Pentium northwood.

If I remove heatsink, at idle, low volts, (LOW TDP) when tjmax of 100C is reached IHS thermocouple reads 95C, because there is no load (minimal TDP) to drive a gradient, so no gradient exists other than minimal across tim1.

Putting heatsink on to cool IHS, placing a load to drive the gradient and the higher the TDP, the higher the gradient given same type of load and other parameters, and you can measure a 27C gradient from IHS to core temp at max TDP. The P4 has same gradient if you test with heatsink on...I tested with heatsink off.

Intel states even in recent slide presentation
"DTS calibration point adjusted higher than target TJUNCTION
– Minimizes potential for PROCHOT# activation below TCASEMAX"

So intel cpu under stock conditions, under max TDP load is designed for throttling DTS=0 at just above tcasemax....to self protect cpu, assuming you do not cheat and raise temps at low TDP by removing heatsink.

If you use tjmax 80 for E8400, than you would have trouble explaining why when IHS temp reads 94C, distance to tjmax is 1 and it is not throttling.... so it is not possible for E8400 tjmax to be less than 95C, nor is it possible to have 100 tjmax with more than 1C DTS sensor offset (effectively same thing as lowering tjmax). Given 4-5C gradient at idle, it has to be 99 to 100C.