How to set up GTL Ref Values for 45nm & 65nm

[mikeyakame]

truehighroller:

If you want to get somewhere, get to know what you are dealing with. There is no success without knowledge....be a real overclocker or leave it be. How do you want to draw your own conclusions if you don't want to know about what's going on on the lowest level while doing low level changes in the BIOS!?

...blind people talking about colors.

Mikeyakame:

I can tell from what you posted that you know your technology. I have had an electronics education myself and I have my devices here like DMM and a solder station of the more expensive kind, but so far I had no ways of taking a look at the in-depth specifications of Intel CPUs. My instinct led me to the following settings:

Q9300 C1/M1 on a ASUS P5Q3 Del. board (P45 based)

FSB: 460, CPU: 3450
VTT: 1.36V
VCore: 1.32V
GTL ref 0/2: 0.69x
GTL ref 1/3: 0.67x
CPU PLL: 1.58V
NB Volt: 1.28V

This puts my GTL references perfectly in the 0.8-1V range. 0.69x1.36V=0.9384V. Tho I wonder if I should try to get closer to 0.90 to have a safety margin.

During my testing phase of this new setup I had some latent instabilities that showed me how well towards stability I was when I was changing the GTL references by giving me more or less frequent calculation errors in Prime 95. This only resolved completely by putting the PCIe frequency from 100 to 101! 101 MHz gives me a way greater range of stable settings.

I've had a lot of hassle with this board, partially due to stupid memory timing defaults that ASUS seems to have taken STRAIGHT from the DDR2 versions of this board.

I seem to be hitting a FSB wall now at a bit above FSB 460.

Is there a way to circumvent it? I have had cases where I could boot the system at 480, but even more should be possible for my chip.

That's it for now.

Keep rolling folks, this is one of the most competent threads I've seen here!

Thanks for the support!

Good to see there's still some people out there who want to know how things work to make things work! It's the fundamental I practice. If I don't understand something in particular I go to extended lengths to figure it out so at the end I can make my life easier and find answers to my questions, so I can pose more!
I have somewhat of an electrical background, my fathers an Electrical Engineer and I just enjoy electronics and mechanics of things! So I suppose I spend a lot of time doing all fun kinds of things from working on cars to working on computers and gizmos!

Now with your question. From my understanding the hole at 455-475ish requires a lot of GTL reference voltage to overcome the extremely small area under the curve that exists at nominal voltage. Your method of fine tuning GTL Ref voltage via Prime95 is spot on, and honestly thats exactly how I do it too. Adjust the multiplier based on calculation error frequency. The later the calculation error occurs the closer to ball park the GTL Reference voltages / multipliers is to nominal for that FSB and CPU frequency.

I've played with a DDR2 P5Q deluxe and it wasn't fun and games, it was one of the most unpredictable and poorly behaved chipsets I've encountered (p45 I mean), but it's by no means not without possibility of being tamed. Just really really irritating for the most part. I'd hate to be dealing with the DDR3 version, but its not so much Asus' fault (except for the horrible memory support) but rather Intel being stuck writing bios code to support speeds way above design specs due to user demand.

At 450MHz on the P5Q I know I was using 0/2 = 0.73x, and 1/3 = 0.715x for a 65nm chip with around 1.34v vTT, might have been 1.36v but its been a while. Perhaps try starting around there and see how that goes, I know this seems quite high but the idea is to move the crossing point where the rising and falling edges of bclk0 and bclk1 meet way above where they nominally should be, to a region where a valid logical 1 can be determined.

It would raise the value of vIH (input high), also raising vOH(output high), and since vIL(input low) and vOL(output low) can exist anywhere from 0.3v below the crossing threshold to 0v for a logical 0 there is plenty of area to determine the switch to ground for a logical 0. Raising vIH on the other hand means from my understanding that since ringback will always occur and at the point of the FSB hole you can shift the ringback margin inside the crossing threshold where it won't interfere in determining a valid logical 1. The excessive ringback occurs due to the amplitude of the voltage? required for those base clock frequencies from what I understand. I still have some gaps but I guess I try and do my best to explain it so it makes sense! Hell even I get confused explaining electrical theory sometimes! It's brain racking!

Any questions just shoot and feel free to drop ideas, theories and knowledge we can use to correlate all the data! The more gaps we fill the better we can get the understanding across to more people!

Thanks again for the kind words!

Edit: I also find PCIE freq of around 101-103mhz or 110-114mhz to work better at above 400FSB too. Not sure why exactly but its possible it's something to do with the way the frequency is divided from the base clock and multiplied from the analog PLL clock generator.