that's validated speed that each speed bin has been tested to run at. Please don't confuse that with achievable speed by this community.
All the speed bins have memory and QPI multies unlocked
The main issue as explained by others, is the potential difference between the memory and controller. The voltage applied to each sets the possible potential that the signaling lines see on each end. Higher voltage on the memory means that there will be some direct current flow towards the memory controller. This is destructive, as these pathways on die are not designed to be able to dissipate excess current. As Tony has said, DDR3 voltages have been inflated for the current 45nm line to help with proper signaling to an aging MCH architecture.
Companies can't really bring out their low voltage lines of memory yet, as they are not optimized for the current Penryn platforms. If what Tony says is true though, most current DDR3 kits may just end up stable at lower voltages when operated through the new memory controller architecture on Nehalem, but we will just have to wait for someone to test this for us.





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