Without full access to bios code and Intel's super secret register documentations they keep us back with I suppose his effort is quite applaudable. Most of the problems with the P45 chipset all come back to the core bios code written by Intel. It was a chipset that was never designed in the first place to do most of the things it is semi-capable of doing now. It's a mainstream chipset aimed at a mainstream market that at present is performing at times on par if not better than the high end X48 chipset which was designed from ground to do what it does. P45 was only ever designed to support a maximum of 1333MHz DDR2/3 and what more it does is cause of Intel's superior knowledge of optimized asm and no doubt impossible feats to make the impossible possible.
Heavy pressure from OE mobo manufactuers for this chipset to work outside it's original design specs has probably resulted in very specific optimized asm routines which I believe are the reason that this is no doubt has become the most impressive generally incompatible and unpredictable chipset in Intel's history. It either works fantastically with certain hardware or fails miserably with others. It's always going to be the case of hit or miss to balance performance Intel pulled out of thin air with wide market component compatibility. Where as chipsets like the X48 since they aim at the smaller high end market don't have to maintain such a broad spectrum of compatibilities since most high end users stick to pretty specific high end hardware which more times than not operate much closer to a common set of specs than mainstream equivalents do. High end memory ic's are limited to only 2 or 3 different memory manufacturers, namely PSC, Samsung and Micron at present.




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