Quote Originally Posted by ether.real View Post
What strikes me as odd is the supposed link between RAM voltage and CPU voltage. That makes no sense to me.
The MCH is on the die and therefore is constructed on a 45nm scale. Isn't the vdimm the voltage used to communicate between the MCH and the modules? If so then pumping 2.1vdimm through a 45nm MCH = deadly like we are currently doing with DDR3 sticks to hit high speeds with tight timings.