Here are my settings for 440x8 266/667 tRD6, 24/7 stable:Originally Posted by carmatic
Raising CPU PLL may lead to a very quick CPU degradation. Also keep your VTT < 1.35V for 24/7.Code:CPU Feature - Thermal Management Control: Enabled - PPM(EIST) Mode: Enabled - Limit CPUID MaxVal: Disabled - CIE Function: Auto - Excecute Disable Bit: Enabled - Virtualization Technology: Enabled - Core Multi-Processing: Enabled Exit Setup Shutdown: Mode 2 Shutdown after AC Loss: Disabled CLOCK VCO divider: Auto CPU Clock Ratio Unlock: Enabled CPU Clock Ratio: 8 - Target CPU Clock: CPU Clock: 440 Boot Up Clock: DRAM Speed: 266/667 - Target DRAM Speed: PCIE Clock: 100mhz PCIE Slot Config: 1X 1X CPU Spread Spectrum: Disabled PCIE Spread Spectrum: Disabled SATA Spread Spectrum: Disabled Voltage Settings CPU VID Control: Auto (1.2325) CPU VID Special Add Limit: Enabled CPU VID Special Add: Auto DRAM Voltage Control: 2.0V SB Core/CPU PLL Voltage: 1.510V NB Core Voltage: 1.504V CPU VTT Voltage: 1.210V Vcore Droop Control: Enabled Clockgen Voltage Control: 3.45V GTL+ Buffers Strength: Strong Host Slew Rate: Weak MCH RON Offset Value: 00 MCH RTT Offset Value: 00 MCH Slew Rate Offset Value: 00 MCH VREF 1 Value: 00 MCH VREF 2 Value: 00 MCH VREF 3 Value: 80 GTL REF Voltage Control: Enabled x CPU GTL1/3 REF Volt: 85 x CPU GTL 0/2 REF Volt: 83 x North Bridge GTL REF Volt: 96 DRAM Timing - Enhance Data transmitting: Fast - Enhance Addressing: Fast - T2 Dispatch: Enabled Clock Setting Fine Delay DRAM CLK Driving Strength: Level 6 DRAM Data Driving Strength: Level 8 Ch1 DLL Default Skew Model: Mode 0 Ch2 DLL Default Skew Model: Mode 0 Fine Delay Step Degree: 5ps Ch1 Clock Crossing Setting: Auto - DIMM 1 Clock fine delay: Current - DIMM 2 Clock fine delay: Current - Ch 1 Command fine delay: Current - Ch 1 Control fine delay: Current Ch2 Clock Crossing Setting: Auto - DIMM 3 Clock fine delay: Current - DIMM 4 Clock fine delay: Current - Ch 2 Command fine delay: Current - Ch 2 Control fine delay: Current Ch1Ch2 CommonClock Setting: Auto Ch1 RDCAS GNT-Chip Delay: Auto Ch1 WRCAS GNT-Chip Delay: Auto Ch1 Command to CS Delay: Auto Ch2 RDCAS GNT-Chip Delay: Auto Ch2 WRCAS GNT-Chip Delay: Auto Ch2 Command to CS Delay: Auto CAS Latency Time (tCL):5 RAS# to CAS# Delay (tRCD):5 RAS# Precharge (tRP):5 Precharge Delay (tRAS):15 All Precharge to Act: 6 REF to ACT Delay (tRFC): 54 Performance LVL (Read Delay) (tRD): 6 Read delay phase adjust: Enter Ch1 Read delay phase (4~0) - Channel 1 Phase 0 Pull-In: Auto - Channel 1 Phase 1 Pull-In: Auto - Channel 1 Phase 2 Pull-In: Auto - Channel 1 Phase 3 Pull-In: Auto - Channel 1 Phase 4 Pull-In: Auto Ch2 Read delay phase (4~0) - Channel 2 Phase 0 Pull-In: Auto - Channel 2 Phase 1 Pull-In: Auto - Channel 2 Phase 2 Pull-In: Auto - Channel 2 Phase 3 Pull-In: Auto - Channel 2 Phase 4 Pull-In: Auto MCH ODT Latency: Auto Write to PRE Delay (tWR): 14 Rank Write to Read (tWTR): 11 ACT to ACT Delay (tRRD): 3 Read to Write Delay (tRDWR): 8 Ranks Write to Write (tWRWR): 6 Ranks Read to Read (tRDRD): 6 Ranks Write to Read (tWRRD): 5 Read CAS# Precharge (tRTP): 3 ALL PRE to Refresh: 6
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