X48 Rampage Formula Preview.

[OVERK|LL]

http://www.xtremesystems.org/forums/...hlight=rampage

It's the best board ever built in terms of OCing. Will cost $450 though.

I can wait for the New X58s and the Intel true Quad Nehalems in 3 months, but Why!

That's 3 months of fun I'll be Depriving Myself Of!!!!



I'll just buy an X58 1366socket Mobo and a Nehalem in 3 months.

I think you may have an addiction

[rodman]

Question about the 2 lan ports. Can I use one of these to connect a Xbox360 to the internet? Wondering why a mobo would have 2 ports when you only need one to connect. I have a cable internet connection. Would be nice not to have to buy a hub/router.

I want to just be able to plug a ethernet cable into Lan2 on the mobo and connect to the net

[OVERK|LL]

Question about the 2 lan ports. Can I use one of these to connect a Xbox360 to the internet? Wondering why a mobo would have 2 ports when you only need one to connect. I have a cable internet connection. Would be nice not to have to buy a hub/router.

I want to just be able to plug a ethernet cable into Lan2 on the mobo and connect to the net

Teaming. You can team the adaptors together and theoretically double the throughput capability of your ethernet connection.

OR

You can connect to two separate LAN's.

You can bridge two separate LAN's.

.....etc.

Lots of scenarios for the use of multiple NIC's.

[rodman]

Teaming. You can team the adaptors together and theoretically double the throughput capability of your ethernet connection.

OR

You can connect to two separate LAN's.

You can bridge two separate LAN's.

.....etc.

Lots of scenarios for the use of multiple NIC's.

So in other words I can not connect a 360 to the other port. Oh well, would have been nice though.

[OVERK|LL]

So in other words I can not connect a 360 to the other port. Oh well, would have been nice though.

WHat are you trying to do with the 360? You could setup NAT on the other port if you want and give the 360 internet access through your computer.

[mikeyakame]

Few things I've learnt so far from my adventures with this board.

Spread spectrum clocking on either pci-e or cpu at above 400FSB will create crosstalk on the Southbridge at certain PLL voltages, and at worst cause display freeze. Disable these.

If you are using a silly high VTT, more than 0.05V above VCC (CPU) to get stability you are more than likely doing something wrong. Raise VNB one or two steps and adjust CPU/NB_GTL_REF ratios up / down, also adjust CPU_PLL raising / reducing 0.02 in steps and keep track of its real voltage in Hardware monitor section in bios. As you adjust this try adjusting VTT other way by 0.02 steps. As you adjust VTT you will need to compensate GTL_REF voltages for either NB/CPU or both. Play with ratios up / down alternatively and pay attention to system response or failure timeframe. If its failed in shorter time you are going wrong way. As you change VTT or VCC, GTL_REF for both CPU/NB will require more frequent adjustment as you go above 450FSB to eliminate power/ground bounce, crosstalk or electrical noise in range of V(IL) and V(IH) from GTL+ reference voltage. Adjusting VTT changes GTL+ reference voltage by ratio of GTL_REF and gives more voltage high or voltage low input headroom for both CPU and FSB clock signal swing between -/+ for rise/fall. Sometimes you may need to adjust DDR_CONTROLLER_REF by 10-20mV higher, and apply 10mv lower value on CHA/CHB, or just leave on auto for self tracking.

SB_PLL (1.5V) tracks CPU_PLL so leave it on auto, crosstalk is a b**** to diagnose.

Patience is a virtue with this board, but it gives nice as hell results when you get things right. Find base values that at least post, note these all down in a book as your base values for that FSB/DRAM freq. Now make minor changes to each value one or two at a time, write down what you changed and whether it was better / worse and do this progressively as you improve results. If you find certain settings to be performing fairly well, use the OC Profile feature and save the OC profile. This way if you go too far off track with adjustments, you can load the OC profile from the point you were going the right direction.

If you adjust DRAM frequency more than 40-50MHz from point you calculated your manually set CLK_SKEWs, they will probably need minor adjustment. I've found that Channel B on mine will need +250PS at 400FSB, and only +50PS at 500FSB, strangely CHA is happy with a delay of 50PS no matter what clocks, must be due to minimal interference on traces.

With 2GB ram sticks, if they are 8 bank then you need to adjust a few memory timing values to create optimal windows for recovery / delay times. Most notably is tRFC (refresh cycle), needs at least a 150% window of the same tRFC with 4 bank dimms (512mb/some 1gb). I find 45-55 tRFC is good for 4 bank dimms, 8 bank needs at least 65-70 for the same cycle.
ALL_PRE_TO_ACT and ALL_PRE_TO_REF timings are auto set for 4 bank, these need to be loosened by 2t, ie 5t -> 7t. This is so the window is large enough for either all read data to be burst off the data bus to the MCH, or write recovery window to be open long enough to write all data to same / diff ranks or banks of each dimm.
Precharge timings should be at least min value of tRP, tRTP should be tRP + 2 (2 is number of clocks delayed before read burst starts)

AI Clock Twister is a fancy pants name Asus uses for what is basically how aggressive or passive the handshake parameters are for data strobes (setup / hold time) between MCH and all DIMM slots. From what I can tell when I adjust CHA/CHB skew -+50PS, Everest shows a non linear change in Dimm 1 - 4 Fine Clock adjustment which sets delay more aggressive in relation to each of the others with strong / stronger. I have read somewhere an Asus engineer did mention in an interview for a magazine it has somewhat of this purpose. Internal MCH / DRAM controller params to minimize or increase idle times / window sizes / strobe duration / strobe skew adjustment. This is probably why there is much more noticed increase in Memory BW when using with Transaction booster.

Transaction booster seems like a programmed intelligent DRAM scheduling for memory transactions between MCH & DRAM controller. Less time spent in idle clocks means more data is throughput as you can increase the amount of successive data strobes for bursting read / writes in the same amount of time it takes for a Row or Refresh cycle. It could also adjust BL (burst latency) between 4 or 8 depending on whether there are successive Reads or combination of Read or Writes.

BL of 4 decreases the amount of clocks required to wait to begin a read burst, but no writes can occur during the same Data strobe with this value. BL of 8 allows for concurrent read / write burst in same strobe at the expense of waiting more clocks to begin the read/write burst and smaller chance of conflict between burst windows for different banks/ranks. Traffic conflicts on the bus inflict the penalty of upto worst case scenario where window becomes too small to complete the transaction in, so timings need to be loosened to allow for the collisions due to commands being issued too early / late or other sub timings being too tight (insufficient window to allow recovery / burst delay) or too loose (overlap where row cycle / ref cycle hasnt completed and successive ones become delayed to the point where transactions cause a traffic jam on the bus and potential conflicts between WE or RD to ranks of memory either completed previously, other rank on same bank may need to be written to while previous rank still being accessed, etc)

I'll add more to this as I find time to document or understand why something happens I cant explain but know how to fix.

[GAR]

http://www.xtremesystems.org/forums/...hlight=rampage

It's the best board ever built in terms of OCing. Will cost $450 though.

I can wait for the New X58s and the Intel true Quad Nehalems in 3 months, but Why!

That's 3 months of fun I'll be Depriving Myself Of!!!!



I'll just buy an X58 1366socket Mobo and a Nehalem in 3 months.

Man, you got some extra money to burn???

[Emperor]

I keep getting this boot problem with this board.

everytime i try 320fsb, I get this boot error.

bios checksum not right.
checking for cd-rom
usb device not found...

and the last 2 lines keep repeating
cpu vcore 1.3
dram 2.2v
fsb strap 266
ram freq 802mhz
multi 7

all these are pretty mild settings. i've previously booted up and ran memtest at 900mhz for rams and 310 for fsb without problems. other than some errors in memtest as i was binning them

[003]

Few things I've learnt so far from my adventures with this board.

Spread spectrum clocking on either pci-e or cpu at above 400FSB will create crosstalk on the Southbridge at certain PLL voltages, and at worst cause display freeze. Disable these.

If you are using a silly high VTT, more than 0.05V above VCC (CPU) to get stability you are more than likely doing something wrong. Raise VNB one or two steps and adjust CPU/NB_GTL_REF ratios up / down, also adjust CPU_PLL raising / reducing 0.02 in steps and keep track of its real voltage in Hardware monitor section in bios. As you adjust this try adjusting VTT other way by 0.02 steps. As you adjust VTT you will need to compensate GTL_REF voltages for either NB/CPU or both. Play with ratios up / down alternatively and pay attention to system response or failure timeframe. If its failed in shorter time you are going wrong way. As you change VTT or VCC, GTL_REF for both CPU/NB will require more frequent adjustment as you go above 450FSB to eliminate power/ground bounce, crosstalk or electrical noise in range of V(IL) and V(IH) from GTL+ reference voltage. Adjusting VTT changes GTL+ reference voltage by ratio of GTL_REF and gives more voltage high or voltage low input headroom for both CPU and FSB clock signal swing between -/+ for rise/fall. Sometimes you may need to adjust DDR_CONTROLLER_REF by 10-20mV higher, and apply 10mv lower value on CHA/CHB, or just leave on auto for self tracking.

SB_PLL (1.5V) tracks CPU_PLL so leave it on auto, crosstalk is a b**** to diagnose.

Patience is a virtue with this board, but it gives nice as hell results when you get things right. Find base values that at least post, note these all down in a book as your base values for that FSB/DRAM freq. Now make minor changes to each value one or two at a time, write down what you changed and whether it was better / worse and do this progressively as you improve results. If you find certain settings to be performing fairly well, use the OC Profile feature and save the OC profile. This way if you go too far off track with adjustments, you can load the OC profile from the point you were going the right direction.

If you adjust DRAM frequency more than 40-50MHz from point you calculated your manually set CLK_SKEWs, they will probably need minor adjustment. I've found that Channel B on mine will need +250PS at 400FSB, and only +50PS at 500FSB, strangely CHA is happy with a delay of 50PS no matter what clocks, must be due to minimal interference on traces.

With 2GB ram sticks, if they are 8 bank then you need to adjust a few memory timing values to create optimal windows for recovery / delay times. Most notably is tRFC (refresh cycle), needs at least a 150% window of the same tRFC with 4 bank dimms (512mb/some 1gb). I find 45-55 tRFC is good for 4 bank dimms, 8 bank needs at least 65-70 for the same cycle.
ALL_PRE_TO_ACT and ALL_PRE_TO_REF timings are auto set for 4 bank, these need to be loosened by 2t, ie 5t -> 7t. This is so the window is large enough for either all read data to be burst off the data bus to the MCH, or write recovery window to be open long enough to write all data to same / diff ranks or banks of each dimm.
Precharge timings should be at least min value of tRP, tRTP should be tRP + 2 (2 is number of clocks delayed before read burst starts)

AI Clock Twister is a fancy pants name Asus uses for what is basically how aggressive or passive the handshake parameters are for data strobes (setup / hold time) between MCH and all DIMM slots. From what I can tell when I adjust CHA/CHB skew -+50PS, Everest shows a non linear change in Dimm 1 - 4 Fine Clock adjustment which sets delay more aggressive in relation to each of the others with strong / stronger. I have read somewhere an Asus engineer did mention in an interview for a magazine it has somewhat of this purpose. Internal MCH / DRAM controller params to minimize or increase idle times / window sizes / strobe duration / strobe skew adjustment. This is probably why there is much more noticed increase in Memory BW when using with Transaction booster.

Transaction booster seems like a programmed intelligent DRAM scheduling for memory transactions between MCH & DRAM controller. Less time spent in idle clocks means more data is throughput as you can increase the amount of successive data strobes for bursting read / writes in the same amount of time it takes for a Row or Refresh cycle. It could also adjust BL (burst latency) between 4 or 8 depending on whether there are successive Reads or combination of Read or Writes.

BL of 4 decreases the amount of clocks required to wait to begin a read burst, but no writes can occur during the same Data strobe with this value. BL of 8 allows for concurrent read / write burst in same strobe at the expense of waiting more clocks to begin the read/write burst and smaller chance of conflict between burst windows for different banks/ranks. Traffic conflicts on the bus inflict the penalty of upto worst case scenario where window becomes too small to complete the transaction in, so timings need to be loosened to allow for the collisions due to commands being issued too early / late or other sub timings being too tight (insufficient window to allow recovery / burst delay) or too loose (overlap where row cycle / ref cycle hasnt completed and successive ones become delayed to the point where transactions cause a traffic jam on the bus and potential conflicts between WE or RD to ranks of memory either completed previously, other rank on same bank may need to be written to while previous rank still being accessed, etc)

I'll add more to this as I find time to document or understand why something happens I cant explain but know how to fix.

Holy . Extremely informative post. I am going to have to look into some of this tomorrow! If you figure anything else out, please post it!

[RealTelstar]

Wondering why a mobo would have 2 ports when you only need one to connect.

Simple answer: i use the second lan to connect my two computers with a crosslink cable. All i can say is that the marvell chip is flawless.

[SergioRoadster]

I can do 450 on my FSB with 1.4v. I also reseated my NB heatsink with AS5 and put an 80mm fan on top of it.

It might be you CPU that needs more voltage, not the NB.

If wasn't much trouble could you or other people reading also with a E8400 and 1066MHZ RAM post their BIOS settings in that 450 FSB range?
Myself been trying overclocking and the maximum I managed was getting the E8400 to 3500MHZ and 3800MHZ, but VIsta gets slow loading.
I'm sorry for bothering with this post, but I'm new on all this. The only thing I used to do was to exchange broken cd drives from my old PC. Last week I bought the parts and after carefully reading I managed to set up my new computer (fortunatly nothing exploded when I made the first boot). You can see how green I am on all this.

One thing about the E8400 voltages. Some say that 1.36V should be the maximum for this CPU, others 1.45V.
In my E8400 box there's a sticker that says "VERSION #: E27439-001 1.25V max".
I'm really confused on which voltage is safe to use.

[3lfk1ng]

If wasn't much trouble could you or other people reading also with a E8400 and 1066MHZ RAM post their BIOS settings in that 450 FSB range?

Already posted for everyone 500mhz is great for a rock solid 1:1 ratio.

[rodman]

Already posted for everyone 500mhz is great for a rock solid 1:1 ratio.

The values you listed, are they taken from hardware monitor under power options? Or are these the values you set in the tweaker menu? I ask becouse the values I set in tweaker are not always the actual values in hardware monitor in bios or otherwise.

For me if I leave PLL and termination to auto, they default to the values you listed anyway. All I ever mess with is CPU/NB and Dram voltage settings as auto sets the rest of them 'correctly' for me.

I can't enable loadline calibration as it will crash out of know where wile web surfing. That may make a diff for my CPU voltage settings.

Oh, does anyone know what value(s) the NB temps are in cpuid harware monitor? Actually a full translation would be most helpfull.

[traveler]

How does one remove the pins on the southbridge so that I can remove the heatsink assembly? (I hope the heatsink comes off easily)

What's the best way to remove/lift the silver finned aluminum part of the northbridge heatsink? (by the I/O panel of the motherboard) It's attatched there somehow.

I have no problem over the northbridge chip itself. The heatsink lifts right off there and I can see a loose square thermal pad in there. (brand new just taken out of the box motherboard)

Please spell it out clearly for me so I can do this. I'd like to replace the thermal material with Ceramique.

[Brama]

Brama tell me if this bios is compatible with raid controllers

I will test this night.
I cross my fingers.....with the 30°+ in my shack, I wish I have not to open my PC.

[Brama]

I will test this night.
I cross my fingers.....with the 30°+ in my shack, I wish I have not to open my PC.

I opened my PC

408 i s like 406, regarding disk controllers

Back to 403

[RealTelstar]

bad, bad asus!

[Shadowthor]

I guess more beta testing is in need, as well as a fix for that issue.

[GAR]

OK so i went ahead and took off the Nb heatsink and put AS5, temps stayed the same so i already had good contact and my max stable fsb is still 427, this is the worst overclocking board i have ever had the pleasure of working with, i have tried everyones settings with no luck, ive even tried my own settings, this is a big mystery to me.

[Kensek]

I did this on My Rampage 3 months ago. Add .03 to VCore since Everest is reading it with thte VDroop.

CPU PLL was 1.56v

Also I skewed the memory in A by +50
and in B by plus +200

And Disabled all Spectrums.

[Kensek]

These are settings from My first X3350. The ones above are from my second one. The second one had a higher Temp variance amongst the 4 CPU Cores.

[GAR]

Lucky, i cant even get my board past 427fsb stable.

[Rickpatbrown]

my max stable fsb is still 427, this is the worst overclocking board i have ever had the pleasure of working with, i have tried everyones settings with no luck, ive even tried my own settings, this is a big mystery to me.

Drop your CPU multiplier and see how high your FSB can go. This mother board is fantastic in my humble opinion. It's just got a lot of settings and needs a lot of attention . . . high maintenance girlfriend . . . but at least you can power it down.

If you still can't hit a decent FSB with a low (I mean like 7x) multiplier, reset CMOS and start over. Sometimes you get so lost in the settings that you need to do this.

[crash2k]

I agree with Rick, you can't hope that you make 450x9, except if you have a good CPU like my Q9650 ES that can be 8hours prime stabile with 467x9!

Even with my excellent Q6600 L737B i couldn't go far with 9 multi, i had to lower to 8 and i could go untill 465mhz, with 7x i had 2hours prime stabile @ 500x7.

try to lower the multi and you will go over 420 for sure.

[stealth]

Lucky, i cant even get my board past 427fsb stable.

Somewhere else is the problem this board can do 590+ FSB,may your ram or the CPU.

I did 550Mhz almost without any tweaking:

http://www.overclockers.gr/vbull/att...7&d=1213565541

stealth