X48 Rampage Formula Preview.

[keichan82]

Did some quick overclocking today:
4.5ghz at 1.456v




Oh...and here is that desktop wallpaper for us Rampage/Maximus users I promised in the OG post.


The photo's credit goes out to my close friend Jeff.

What voltage? core temp?

[GAR]

I still cannot go over 400fsb with my setup, this is crazy!!!

[bigslappy]

I still cannot go over 400fsb with my setup, this is crazy!!!

I can & we have about the same setup
i got bios 406 the beta

[GAR]

I can & we have about the same setup
i got bios 406 the beta

Yeah its very strange, once i hit 450, prime fails instantly, even with 0406 bios

[OVERK|LL]

Yeah its very strange, once i hit 450, prime fails instantly, even with 0406 bios

I was/am having a similar issue with mine; it won't remain stable at 450x8 or 400x9. Looks like it's northbridge temp.

Funny part is, at 430x8, it's problem-free????? All voltages are can remain in the green and it's prime-stable without issue on both small FFT's and BLEND.

[Rickpatbrown]

I was/am having a similar issue with mine; it won't remain stable at 450x8 or 400x9. Looks like it's northbridge temp

What are your temps and Voltages?

[OVERK|LL]

What are your temps and Voltages?

I'm at 430x8 right now (100% prime stable) with
CPU Voltage 1.475 (BIOS, it's ~1.43 in Windows)
CPU PLL of 1.5
Northbridge at 1.49
FSB Term is 1.4
DRAM is at 2.0
SB is 1.05
CPU GTL Ref is 0.67x
NB GTL Ref is 0.67x

Current CPU Temp is low 50's (52,49,54,52) with SETI and WCG running
Current NB Temp is 39

But when I went for 450x8, or 400x9, I had to bring up the voltages which caused NB temp to creep into the 60's!!!!!!

[Rickpatbrown]

I can do 450 on my FSB with 1.4v. I also reseated my NB heatsink with AS5 and put an 80mm fan on top of it.

It might be you CPU that needs more voltage, not the NB.

[OVERK|LL]

I can do 450 on my FSB with 1.4v. I also reseated my NB heatsink with AS5 and put an 80mm fan on top of it.

It might be you CPU that needs more voltage, not the NB.

I got up into the high 1.5x's with the CPU trying to get it stable. I said screw it. The NB voltage didn't get all that high; 1.55v, but it got HOT.

I hadn't reseated it, and it's not getting ideal airflow either. I have an AMD CPU fan overtop of my RAM, which I will adjust to push more air over the NB when I get some double sided tape. We'll see how this affects the temps.

[DEFLORATOR]

I was/am having a similar issue with mine; it won't remain stable at 450x8 or 400x9. Looks like it's northbridge temp.

Funny part is, at 430x8, it's problem-free????? All voltages are can remain in the green and it's prime-stable without issue on both small FFT's and BLEND.

Who on earth promised to you that your Q6600 would be stable at 3600 MHz?? If it's stable at 3400, it doest mean it will go next +200 Mhz, even with vcore increase.

[mikeyakame]

Lowest latency I got around to coercing at 485FSB.


Stress testing, memset timings and Everest sensor page data ;>


My bios settings to do this stable.

AI Overclock Tuner.............................. Manual
CPU Ratio Setting............................... 7.0
FSB Strap to North Bridge....................... 333MHz
FSB Frequency................................... 485MHz
PCI-E Frequency................................. 105MHz

DRAM Frequency.................................. DDR2 - 1165Hz
DRAM Command Rate............................... 2N
DRAM CMD Skew on Channel A...................... AUTO
DRAM CMD Skew on Channel B...................... AUTO
DRAM CLK Skew on Channel A...................... Delay 50ps
DRAM CLK Skew on Channel B...................... Advance 250ps
DRAM Timing Control............................. Manual
Primary Timings
CAS# Latency................................ 5T
RAS# to CAS# Delay.......................... 5T
RAS# PRE Time............................... 5T
RAS# ACT Time............................... 16T
RAS# to RAS# Delay.......................... 4T
REF Cycle Time.............................. 50T
WRITE Recovery Time......................... 7T
READ to PRE Time............................ 4T
Secondary Timings
READ to WRITE Delay (S/D)................... 8T
WRITE to READ Delay (S)..................... 5T
WRITE to READ Delay (D)..................... 7T
READ to READ Delay (S)...................... 4T
READ to READ Delay (D)...................... 6T
WRITE to WRITE Delay (S).................... 4T
WRITE to WRITE Delay (D).................... 6T
Tertiary Timings
WRITE to PRE Delay.......................... 14T
READ to PRE Delay........................... 5T
PRE to PRE Delay............................ 1T
ALL PRE to ACT Delay........................ 6T
ALL PRE to REF Delay........................ 6T

DRAM Static Read Control........................ Disabled
AI Clock Twister................................ Stronger
AI Transaction Twister.......................... Manual

Common Performance Level.................... 07
Pull-In of CHA PH1.......................... Disabled
Pull-In of CHA PH2.......................... Disabled
Pull-In of CHA PH3.......................... Disabled
Pull-In of CHA PH4.......................... Disabled
Pull-In of CHB PH1.......................... Disabled
Pull-In of CHB PH2.......................... Disabled
Pull-In of CHB PH3.......................... Disabled
Pull-In of CHB PH4.......................... Disabled

CPU Voltage..................................... 1.40000V
CPU PLL Voltage................................. 1.68V
Northbridge Voltage............................. 1.53V
DRAM Voltage.................................... 2.24V
FSB Termination Voltage......................... 1.30V
South Bridge Voltage............................ 1.175V
SB 1.50V Voltage................................ 1.65V
Loadline Calibration............................ Enabled
CPU GTL Voltage REF............................. 0.67x
NB GTL Voltage REF.............................. 0.63x
DRAM Controller Voltage REF..................... DDR_REF - 10mV
DRAM Channel A Voltage REF...................... DDR_REF + 10mV
DRAM Channel B Voltage REF...................... DDR_REF

CPU Spread Spectrum............................. Disabled
PCI-E Spread Spectrum........................... Auto

In case you are wondering why im using 7x multi, mainly because the TT 750W j0nx PSU I've got in at the moment (for sake of 8 pin PCI-E for stupid GTX280) gives up the ghost when I try and push more than 3.4GHZ at greater than 1.41V vCPU in the bios. Hopefully I'll find time at the end of the week to go out and pick up a Corsair 1000W PSU if my hectic work timetable permits.

[Brama]

DRAM CLK Skew on Channel A...................... Delay 50ps
DRAM CLK Skew on Channel B...................... Advance 250ps

Above data are calculated theoretically or you tested several values and find these the best?

[OVERK|LL]

Who on earth promised to you that your Q6600 would be stable at 3600 MHz?? If it's stable at 3400, it doest mean it will go next +200 Mhz, even with vcore increase.

HHAHHAHHAA, nobody promised me! I was just quite hopeful that it would And it only needs to go 150Mhz

[mikeyakame]

DRAM CLK Skew on Channel A...................... Delay 50ps
DRAM CLK Skew on Channel B...................... Advance 250ps

Above data are calculated theoretically or you tested several values and find these the best?

Little guess work, rest practical application. Lots of memory testing / intel linpack stressing. It's the clock skews which at tightest timings/highest dram clocks that gave no errors and best performance / lowest latency. But usually there will be a delay on Channel A since its closest to CPU, and advance on Channel B since the trace lengths are longer than Channel A. You can kind of tell which way timings need to be skewed especially on quad cores by how data is queued to each cpu die.

Every board is a little different, but correct dram/mch skews shouldnt be too far off for any given board.

[Rickpatbrown]

You can kind of tell which way timings need to be skewed especially on quad cores by how data is queued to each cpu die

How can you tell how data is being queued to each CPU?

How fast does an electrical signal travel along a trace?

[RealTelstar]

What is the suggestion for pci-e frequency?
Because i have a raid card on the second slot i'm afraid to raise it.

[mikeyakame]

Don;'t go too much higher than 105. That should be safe, I found using PCI-E spread spectrum set to auto helps a little with data transfer speeds and consistency when using an optical drive.

[mikeyakame]

How can you tell how data is being queued to each CPU?

How fast does an electrical signal travel along a trace?

Well considering we are using picasecond skews, i'd take a wild guess and say pretty damn fast. Depends on DRAM frequency, timings, etc, considering if a 50PS adjustment can make or break above 450FSB for me, and in skew clocks at least within a -+ 50 picasecond window which are the diff between 2+ cores failing in prime, etc and a run which you stop with success rather than failure tells me its incredibly fast and requires more and more accuracy with high fsb clocks / more clocks. 50PS adjustments are too coarse, I need 5-10PS where I am at now...Minor adjustments to ref voltages helps skew a little but it's too hit and miss.

Queueing, I don't know if you'd call this an exact method but it's proved to be extremely accurate every time for me once I knew what to look for. Using Intel Linpack Maths Kernel 64-bit benchmark with a problem of dimensions large enough to take up at least 50% ram, and run 4 - 5 tests. I graph each CPU core's load with rivatuner and also watch it with (sounds stupid I know) a vista gadget called ALL CPU Meter. Funny enough this is actually true! Once you get the feel of what is working well, and what isnt you can eye the load of each core, and roughly look at the difference between when each core load suddenly rises rapidly, and then the next and so on, then you watch when it falls, and take note of what the others are doing. Just reading what I wrote it sounds like it could never give you enough data to draw conclusions off, but after all the long nights of tuning, benching, testing, then repeating I've sorta figured out the cues different instabilities will demonstrate when they aren't quite bad enough to cause errors or crashes, but enough to create slices of idle time where there is heavy queueing, inconsistent rendering and poor SB performance, MCH clocks too advanced compared to the CPU clocks, etc.

SHoot me a private message if you got any more questions about my insane methodologies!

I really need to see a mate and grab his oscilloscope for a few weeks to see how close my results are, and fine tune them farther/figure out where i went wrong.

[Brama]

How fast does an electrical signal travel along a trace?

It depends on PCB material.
Normally it is (light speed*speed coefficient of material). On normal PCBs the speed coefficient is about 0.85.

The signals travel at 85% of light speed on a normal PCB, roughly.

It is about 25 cm every ns, 0.25 mm/ps.

The difficult is that the lines are powered by an RF signal at about 500 MHz and the electrical lenght of the path (so the difference in lenght between channel A and channel B) is depending on the frequency and the impedance of the lines.

So the adjustement of skew has to be done in different way at any RAM frequency.

[panheimer]

Hy to everyone!
I'm new in this thread, and just bought this board yesterday, after two weird experience with dfi lt680 and msi p7n diamond...i've decided to throw my bfg 8800 ultra oc away and try intel chipsets.
Well the first experience is just amazing! Put in a Q6700, flashed to the 0406 beta bios, entered bios, set 360x10, 1.45 cpu volt, 2.3 on ram volt, performance level 5 et voilà: an easy 3.6 ghz CPU clock and RAM at 1152 5-5-5-15 2t.
I've run a short prime95 blend test of 4 hrs, and then played all night long with Devil May Cry 4 and GRID with no issue.
But this afternoon, when i've pressed the on button the lcd poster was stuck at "det ram" message. I've powered it off an on and it got recovered from a bad oc? So i entered bios, checked values i've setted before, hit f10 and everything worked fine (but the lcd poster light still remained lit on..). After dinner tried to turn it on again, and got the same cold boot issue but this time no bad oc recovering messages. Again, once entered windows the system worked fawless - except for the lcd poster wich was stuck at "en setup" message with the light lit on - even if i've set it off in bios).
So what's going on? Is a really bad oc? Probably it is so, as i've spent no more than 5 minutes with this, but the system never crashed or freezed...
And the strange lcd poster behaviour is wrong settings symptoms?
Thank you.

[crash2k]

hi guys,
i'm testing my new Q9650 "ES" on the Rampage Formula, i've found my stable setup at 467x9 with 1,36volts. are my settings "safe" for a daily use of a 45nm? i'm with CPU PLL @ 1.54 (bios value), FSBT @ 1.36 in bios = 1.26 in HW monitor and everest, CPU GTL @63x. Temp MAX 61-61-60-60 °C, in average it is 54-56°C.

As i've read around here in XS and in other forums i'm into the safe values to keep the cpu safe, can you confirm?


AI Overclock Tuner.............................. Manual
CPU Ratio Setting............................... 9.0
FSB Strap to North Bridge....................... 333MHz
FSB Frequency................................... 467MHz
PCI-E Frequency................................. 101MHz

DRAM Frequency.................................. DDR2 - 1120MHz
DRAM Command Rate............................... 2N
DRAM CMD Skew on Channel A...................... AUTO
DRAM CMD Skew on Channel B...................... AUTO
DRAM CLK Skew on Channel A...................... Delay 300ps
DRAM CLK Skew on Channel B...................... Advance 300ps
DRAM Timing Control............................. Manual
Primary Timings
CAS# Latency................................ 5T
RAS# to CAS# Delay.......................... 5T
RAS# PRE Time............................... 5T
RAS# ACT Time............................... 15T
RAS# to RAS# Delay.......................... AUTO
REF Cycle Time.............................. AUTO
WRITE Recovery Time......................... 11T
READ to PRE Time............................ 4T
Secondary Timings
READ to WRITE Delay (S/D)................... AUTO
WRITE to READ Delay (S)..................... AUTO
WRITE to READ Delay (D)..................... AUTO
READ to READ Delay (S)...................... AUTO
READ to READ Delay (D)...................... AUTO
WRITE to WRITE Delay (S).................... AUTO
WRITE to WRITE Delay (D).................... AUTO
Tertiary Timings
WRITE to PRE Delay.......................... AUTO
READ to PRE Delay........................... AUTO
PRE to PRE Delay............................ AUTO
ALL PRE to ACT Delay........................ AUTO
ALL PRE to REF Delay........................ AUTO

DRAM Static Read Control........................ Disabled
AI Clock Twister................................ Lighter
AI Transaction Twister.......................... Manual

Common Performance Level.................... 07
Pull-In of CHA PH1.......................... Disabled
Pull-In of CHA PH2.......................... Disabled
Pull-In of CHA PH3.......................... Disabled
Pull-In of CHA PH4.......................... Disabled
Pull-In of CHB PH1.......................... Disabled
Pull-In of CHB PH2.......................... Disabled
Pull-In of CHB PH3.......................... Disabled
Pull-In of CHB PH4.......................... Disabled

CPU Voltage..................................... 1.375...V (1.36 in HW monitor)
CPU PLL Voltage................................. 1.54V
Northbridge Voltage............................. 1.55V (1.53 in HW monitor)
DRAM Voltage.................................... 1.90V
FSB Termination Voltage......................... 1.36V (1.26 in HW monitor)
South Bridge Voltage............................ 1.1V (1.07 in HW monitor)
SB 1.50V Voltage................................ 1.5V
Loadline Calibration............................ Enabled
CPU GTL Voltage REF............................. 0.63x
NB GTL Voltage REF.............................. 0.67x
DRAM Controller Voltage REF..................... DDR_REF
DRAM Channel A Voltage REF...................... AUTO
DRAM Channel B Voltage REF...................... AUTO

CPU Spread Spectrum............................. Disabled
PCI-E Spread Spectrum........................... Disabled

[3lfk1ng]

For those with an E8400/E3110/E8500 looking for a quick 4.25ghz with 1:1 ram timing on their Rampage Formula:

CPU Ratio - 8.5
FSB Frequency - 500
CPU Voltage - 1.4v
CPU PLL Voltage - 1.6v
NB Voltage - 1.35v
DRAM - 2.10 to 2.12 (depends on your ram)
FSB Termination - 1.4v

That is all I changed on my motherboard to get to 24/7 OCCT stable 4.25ghz.

Best of luck to everyone.

[mikeyakame]

It depends on PCB material.
Normally it is (light speed*speed coefficient of material). On normal PCBs the speed coefficient is about 0.85.

The signals travel at 85% of light speed on a normal PCB, roughly.

It is about 25 cm every ns, 0.25 mm/ps.

The difficult is that the lines are powered by an RF signal at about 500 MHz and the electrical lenght of the path (so the difference in lenght between channel A and channel B) is depending on the frequency and the impedance of the lines.

So the adjustement of skew has to be done in different way at any RAM frequency.

The difference in necessary skewing at RAM frequencies not too far from each other, i've found is at most -+50PS. There should be two values to base correct skews off, the other is the physical trace paths on the board. You need to figure this part out first, to use as base/reference values for your particular boards characteristics and response to advancing/delaying.

The rampage has a few valuable skew adjustments which are missing as well as the archaic AGTL+ ref voltage adjustment. There is at least a few cases where to overcome ground and power bounce between rising and falling edges of clocks the ratio of GTL+ REF to VTT will be 0.80-0.90x, notably around 450FSB hole region. Custom ratio 0.40-0.90x maybe even in 2-3% increments would be good enough. Quad cores have 4 Reference voltages, 2 for each die. If we could at least set the GTL Ref for each die that would be gold. Invidual Address / Data GTL+ input skewing per die would be quality. I've come across a couple of my own situations where either die is slightly out of phase with mch/dram but the other is in phase. It's like banging your head against a wall. Minor voltage adjustments help bring clocks in skew finely, but also domino effect sometimes.

[SirDaemon]

For those with an E8400/E3110/E8500 looking for a quick 4.25ghz with 1:1 ram timing on their Rampage Formula:

CPU Ratio - 8.5
FSB Frequency - 500
CPU Voltage - 1.4v
CPU PLL Voltage - 1.6v
NB Voltage - 1.35v
DRAM - 2.10 to 2.12 (depends on your ram)
FSB Termination - 1.4v

Thanks 3lfk1ng

Flashed to bios 0406, loaded setup defaults, and then used your settings and it worked fine. Except i'm using 8x for 4ghz.

I'll keep testing and maybe lower some of the voltage. Maybe CPU PLL? Or FSB Termination.

BTW, i'm using a e8400, mushkin redline pc8000 2x2gb.

[3lfk1ng]

No, thank you. Glad to hear that it will work for others.

More Progress on the Air Cooling front:
4644ghz