AMD 45nm Deneb Pictures, CPU-Z and Super Pi Results

[Donnie27]

Trying to draw parallels to other apps from Super pi is pretty lame to say the least. Especially when even the 12% increase still sucks for this one app.

There is no one SINGLE performance measurement and Yorkfield can out do Phenom from 2 to 40% and is fully app Dependant!

[Epsilon84]

You do have a point about the general tendency of fans over-hyping something before it launches, and I'm not just talking about Deneb either. It appears a lot of people here seem to think a 12.5% increase in SuperPi means even bigger increases in real world apps, when in fact gains in SuperPi are generally exaggerated when compared to real world gains.

I wonder if its possible to disable the L3 on a Phenom? If it is, someone should disable it and see what kind of impact the L3 has on SuperPi times.

[savantu]

...

Now considering we are comparing a Phenom w/2MB L3 with a Deneb w/6MB L3, could it be possible that the majority of the performance increase is down to the much larger cache?

Well , it's fairly obvious the larger L3 is behind the 12% increase.

However , looks like the L3 is still running at low frequency ( 1.8GHz ) , in fact even lower than the 65nm K10 ( 2GHz ).Is it possible they improved the latency ? I doubt it.Increasing the cache typically adds a few cycles of latency.
So , the end result might a a 3x increase in size and slightly slower.

I'll stick by my prediction , 2-7% clock/clock vs. 65nm K10 , Kentsfield like performance.

As for frequency gains , those are misleading at best. AMD demoed 3Ghz 65nm K10 , too bad it needed 1.58V to operate and in the end you can't go over 1.3V in shipping silicon on 65nm => 2.6Ghz tops.

The 45nm 3.4GHz OC uses same amount of voltage ; I'd say 2.8GHz ( as some rumor sites said ) will be the shipping frequency.

[mAJORD]

I find it interesting that everyone is pointing towards the L3 as the reason. When, IIRC a bucketload of people accused the mere existence such a 'slow' L3 cache to be a hinderence to any single threaded performance..

I wonder if these same people will suggest Propus (with no L3) will be even faster than this @ super pi?

[savantu]

I find it interesting that everyone is pointing towards the L3 as the reason. ..

What is the reason then for the 12% gain ? Enlighten us.

[Solus Corvus]

Oh look, the usual battle lines have already formed up. How tiring.

It's faster in superPI, that's great...for SuperPI users. As for me, I will be interested in seeing how it performs in applications I use daily relative to whatever else is available at the time.

[FlanK3r]

I'd agree. If it was a 12.5% jump in something other than SuperPi, I would have been really impressed. However, SuperPi is quite sensitive to cache size, and a 12.5% boost in SuperPi generally does not correlate to same increase in most real world applications, unless the application was also very cache dependant. For example, when comparing C2Ds of different cache sizes we get:

( Source )
E6600 (4MB L2) @ 3.5GHz ~14.7 secs
E6400 (2MB L2) @ 3.5GHz ~16 secs

An E6600 is ~9% faster than an E6400 per clock in SuperPi, but the real world difference between the two is actually only ~3.5%.

Now considering we are comparing a Phenom w/2MB L3 with a Deneb w/6MB L3, could it be possible that the majority of the performance increase is down to the much larger cache?

But structure Core and K10 are different. And for old benchmark Superpi is not working load L3. Its only for L1 to L2 (better is cinebench and for dual-quad CPUs wprime)

[mAJORD]

What is the reason then for the 12% gain ? Enlighten us.

Don't ask me, I'm just putting out there the fact that people's 'expert' opinions are conflicting.

I don't know how Super pi runs, what the cache access is like, Perhaps it's a combination of minor arch improvments, cache latency (L2 still had room for improvement on Agena/barc) AND the L3 size.

[savantu]

Don't ask me, I'm just putting out there the fact that people's 'expert' opinions are conflicting.

I don't know how Super pi runs, what the cache access is like, Perhaps it's a combination of minor arch improvments, cache latency (L2 still had room for improvement on Agena/barc) AND the L3 size.

In Core products , going from 1 to 2 and then 4 MB L2 translate in a few % gains.

It's not inconceivable that increasing the L3 from 2 to 6MB can bring 12%.

[DoubleZero]

I'll take it from the Intel fanboys posts, that now everyone will agree superPI is worthless

[bowman]

Time to ditch the K10Burst, AMD. This isn't going to cut it anywhere but the low end. A minor increase, and a clock speed which can't be sustained (1.4V, 45nm? How long would that last?).

Such a shame.. Third AMD build now, very happy, it's shame they were only able to keep up and beat them for so long. Time to invest in R&D rather than pleasure trips for Ruiz and his cronies.

[Extelleron]

Time to ditch the K10Burst, AMD. This isn't going to cut it anywhere but the low end. A minor increase, and a clock speed which can't be sustained (1.4V, 45nm? How long would that last?).

Such a shame.. Third AMD build now, very happy, it's shame they were only able to keep up and beat them for so long. Time to invest in R&D rather than pleasure trips for Ruiz and his cronies.

You do realize that this CPU is an early sample of the C0 stepping? It is the same stepping AMD showed off in March to the press. It is the first 45nm stepping. You can definitely expect better by the time that these CPUs are actually released.

Just look at Agena's improvement.... B2 couldn't hit more than 2.6GHz reliably, now the B3's can hit 3GHz+ on average. Considering this is the first stepping of Deneb, it is conceivable that it could improve very significantly before release.

[Rammsteiner]

lol still bringing this "native" marketing crap.

How is it crap. Instead of being limited to a poor OC'ing core on a quad core you can get the best out of it.

With all due respect achieving such a speedup in a canned benchmark rarely translates to real world performance, a point I'm sure you appreciate. As terrace215 suggests the increase could purely be due to the larger cache, taking what amounts to pre-lunch hype at face value usually leads to dissapointment. The superpi figures are interesting but without more system level test results, proclaiming AMD IS BACK!!! at this point is premature.

AMD never left tbh.

And yeah, SuperPI sucks, however since AMD didnt do so well lately in that benchmark it's good to see this improvement. But due to L3 cache? Nah. It will have a role though, but not like that.

I'd agree. If it was a 12.5% jump in something other than SuperPi, I would have been really impressed. However, SuperPi is quite sensitive to cache size, and a 12.5% boost in SuperPi generally does not correlate to same increase in most real world applications, unless the application was also very cache dependant. For example, when comparing C2Ds of different cache sizes we get:

( Source )
E6600 (4MB L2) @ 3.5GHz ~14.7 secs
E6400 (2MB L2) @ 3.5GHz ~16 secs

An E6600 is ~9% faster than an E6400 per clock in SuperPi, but the real world difference between the two is actually only ~3.5%.

Now considering we are comparing a Phenom w/2MB L3 with a Deneb w/6MB L3, could it be possible that the majority of the performance increase is down to the much larger cache?

No. L2 cache quite something else than L3 cache, and also a lot faster.

I guess the L3 improvement would only be worth for 5% of the increase.

To him, AMD is back no matter what they sell.

Deneb is being over-hyped and being setup for failure. Trying to draw parallels to other apps from Super pi is pretty lame to say the least. Especially when even the 12% increase still sucks for this one app.

There is no one SINGLE performance measurement and Yorkfield can out do Phenom from 2 to 40% and is fully app Dependant!

As said before, AMD never left. No clue what you're on about.

Anyway, Deneb over-hyped? Super PI lame benchmark? Did the world turn upside down when I was sleeping or what.

Oh well, luckily Nehalem isnt over-hyped. Or even Intel for that matter. And to be honest, I think you might be mistaken a little bit with your Yorkfield > Agena thingy. Unless you could justify the sick prices of Intel's enthusiast aimed CPU's.

What is the reason then for the 12% gain ? Enlighten us.

What about real engineering? The will not to sink the boat? Adding a little bit of cache like Intel did the past few years here and there... It's not all about that really. Tweaking things etc, like a program. There's always a little thing that could be optimized.

I'll take it from the Intel fanboys posts, that now everyone will agree superPI is worthless

You're my hero.

Indeed, spoken about hypocricy, unbelievable. Im not a Super PI fan, but this is just ridiculous.

So what benchmark is lame next? 3DMark because Agena managed to hit the same score as Yorkfield did?

Anyway, Im patiently waiting for C1

[Macadamia]

Geez, does it have to be L3 size? I don't even think that increasing L3 speeds helps the old Phenoms in SuperPi. At all.

L3 is just too much of a hierachy to impact a single threaded test that much. They might have improved L3 reducing overall latency of the whole cache system, but my bet is that L2 is worked on just as much (especially latencies).

L2 is more of a key than L3 here IMO.

[Rammsteiner]

Geez, does it have to be L3 size? I don't even think that increasing L3 speeds helps the old Phenoms in SuperPi. At all.

L3 is just too much of a hierachy to impact a single threaded test that much. They might have improved L3 reducing overall latency of the whole cache system, but my bet is that L2 is worked on just as much (especially latencies).

L2 is more of a key than L3 here IMO.

I dont know how Super PI is calculated by the CPU, but if it matters anyway, I dont even think Super PI is that big it needs to be written on the L3 cache?

I think back ground applications will be switched to L3 and Super PI will be ran of L1 and L2 mostly, maybe a little of L3.

As I said, I cant tell for sure but I highly doubt Super PI has much to do with L3 there.

[Bandwidth]

I'm not sure about SuperPI, don't care for it really. But AMD mentioned Deneb will have some (minor) tweaks compared to Phenom, to improve IPC. So the gain is probably not only from the L3 cache.

There will probably be some programs/games etc that will like the 3x increase in L3 cache size, gaining anywhere from 5-20% just from the L3 alone. Others may not gain much because of the L3 size increase.

Overall I'd say with the minor tweaks, larger L3, and hopefully faster NB speed (lower latency), Deneb can be 10-15% faster than Phenom. As for OC ability, my guess is add about 15-20% more clocks compared to what people are getting now with Phenom.

Just to give an example: Max stable Phenom OC 3GHz * (0.2) = 0.6 + 3GHz = 3.6GHz stable Deneb OC. And as is always the case with AMD, the first batch of new CPUs may not be that special, but later steppings improve a lot (higher frequency, better OC, less heat, less power consumption).

AMD should hurry and release those babies

[Glow9]

When are these supposed to come out anyways is there any timeline?

[Donnie27]

I'll take it from the Intel fanboys posts, that now everyone will agree superPI is worthless

Why? I've said most synthetic BM apps are used for the wrong reason, Add 3D Bung-holi-o Marks while your're at it.

[Mechromancer]

As was said earlier, SuperPi is a test that K10 architecture traditionally did poorly on. If it can manage a 12.5% increase in that test then its safe to say we'll see at least that kind of increase across the board. Also, this test was done on a lowly SB600 mobo. A 790FX+SB750 motherboard with Deneb will likely yield excellent overclocks. What I'm saying here isn't all speculation if you look at the previous 8 months of K10 tests, new SB750 tests and this recent test. AMD promised a 10% to 15% performance gain with Deneb over the original K10 and it looks like they have achieved this claim. SB750 was solely created to provide higher, more stable overclocks. All in all, AMD is headed in the right direction to keep their head above water this round.

The confirmation that AM3 CPUs will be backwards compatible with socket AM2/+ was the icing on the cake. An AMD build will certainly have some longevity.

[terrace215]

As was said earlier, SuperPi is a test that K10 architecture traditionally did poorly on. If it can manage a 12.5% increase in that test then its safe to say we'll see at least that kind of increase across the board.

Um, no.

SuperPi is precisely the kind of test that benefits from increased cache. If anything is safe to say, it is that this would be close to an upper limit of increase one might expect, NOT a lower limit.

You got it 100% backwards.

[surfinhicdude]

I thought someone disassembled SuperPi on this forum not too long ago, and found out that the performance difference between Intel and AMD chips didn't have as much to do with cache sizes as most people think. The parity came from SuperPi making use of mostly x87 legacy instructions, which are quite a bit faster for whatever reason in Intel chips. Perhaps something else in the chip has changed which is providing the boost, or the added cache is only partly responsible. Maybe someone will leak a run with the cached disabled, or for that matter, a more useful benchmark. SuperPi is such a small program, does it even need to write to L3?
By the way, great forums you guys have here!

[JohnZS]

Well , it's fairly obvious the larger L3 is behind the 12% increase.

However , looks like the L3 is still running at low frequency ( 1.8GHz ) , in fact even lower than the 65nm K10 ( 2GHz ).Is it possible they improved the latency ? I doubt it.Increasing the cache typically adds a few cycles of latency.
So , the end result might a a 3x increase in size and slightly slower.

I'll stick by my prediction , 2-7% clock/clock vs. 65nm K10 , Kentsfield like performance.

As for frequency gains , those are misleading at best. AMD demoed 3Ghz 65nm K10 , too bad it needed 1.58V to operate and in the end you can't go over 1.3V in shipping silicon on 65nm => 2.6Ghz tops.

The 45nm 3.4GHz OC uses same amount of voltage ; I'd say 2.8GHz ( as some rumor sites said ) will be the shipping frequency.

I think 3.0Ghz would be likely?
but not much over this I don't think...besides why is everyone so excited in this here thread?
It's not an earth shattering SuperPi result... 45nm Core2 Quad is 9 to 10 seconds faster depending on whether you are on XP or Vista

[perkam]

45nm + DDR2 boards should be interesting. But the Phenom chips need the extra memory bandwith, so DDR3 + 45nm + SB 800 is where its at.

It will be interesting to see how high AMD can clock these though. Hopefully the price cuts on the QX9x50s come soon, so that we can see 2.6Ghz 45nm Phenoms going against the Q9450 at $266 and a 2.8Ghz model battling the Q9550 at the $316 mark. That should put the 2.5 and 2.4ghz Phenoms squarely under $250, forcing the 2.1 and 2.2Ghz models to dip below $200


Perkam

[Kingcarcas]

Nice, looks like AMD is getting on the right track. Hopefully they pwn Intel like they did to Nvidia, price/performance while they release uber expensive chips.

[purecain]

wow these threads used to be extremely informative, in the last few years disrespecting other peoples oppinions have become the norm... A mod needs to get the banning stick out...

really pleased amd are moving forwards... lets hope denab gets even more refined and cores are released that can hit 4ghz.... i'm really impressed with amd's improvements of their chipsets...

cant wait to build an amd based rig....