Thanks for the tips, and all the tips you gave in this thread
Playing with skews did the trick, but I had to set all subtimings by hand.
This is what I came up so far (still tweaking subs), it's Primed and Memtest passed![]()
1st Information:
CAS# Latency: 5
DRAM RAS# to CAS# Delay: 5
DRAM RAS# Precharge: 5
DRAM RAS# Activate to Precharge: 15
RAS# to RAS# Delay : 6
Row Refresh Cycle Time: 55
Write Recovery Time: 6
Read to Precharge Time: 6
2nd Information :
READ to WRITE Delay (S/D): 9
Write to Read Delay (S): 4
WRITE to READ Delay (D): 15
READ to READ Delay (S): 5
READ to READ Delay (D): 7
WRITE to WRITE Delay (S): 5
WRITE to WRITE Delay (D): 7
3rd Information :
WRITE to PRE Delay: 15
READ to PRE Delay: 6
PRE to PRE Delay: 2
ALL PRE to ACT Delay: 7
ALL PRE to REF Delay: 7
DRAM Static Read Control: Disabled
DRAM Read Training: Disabled
MEM. OC Charger: Enabled
AI Clock Twister: Moderate
AI Transaction Booster: Manual
Common Performance Level: 08
All Pull-Ins: Disabled
Now we are getting somewhere
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