http://download.intel.com/technology...Technology.pdf
Some nitpicks :
Put it simply : the process rocks compared to their own 65nm.High-k and metal aren't the only "goodies" put in the mix.Well , Intel recently posted info about its 45nm process.Systematic cross wafer ring oscillator frequency variation slightly lower in 45 nm while random cross wafer variation reduced by about 50%. Mean cross die Vt variation reduced from 20 mV for 65 nm to 11 mV for 45 nm for NFETs and from 9 mV to 7 mV for PFETs.
IBM had less than 20% yeilds on Cell , 200mm^2 logic only.G200 is 450mm^2 and logic only.I'd be surprised if TSMC yields on it are better than 20%.The "horrible yield" card is played far to offen in the recent days, but we'll see when NV brings it 55nm shrink of the G200.
Fortunately , I think they can save most parts and sell then as inferior chips , with disabled paths.






Bookmarks