Quote Originally Posted by LordEC911 View Post
AIW was killed awhile ago...
It shouldn't be missed.


Shared memory is most likely clamshell mode for GDDR5.


I take it you understand the whitepaper?

Why would it need to be "implemented" on the board?
Clamshell mode for GDDR5 does not do what you say it does. Clamshell mode allows for a single memory controller to access 2 memory chips, it does not allow for 2 memory controllers to access a single chip. So no shared memory through clamshell mode because a single memory chip can only cope with 1 controller and not 2, which is need for your shared memory approach.
Basically clamshell mode allows you to use the same 512Mbit chip for both a 512MB 256-bit card using 8 chips and a 1GB 256-bit card using 16 chips. That's also what spursindonesia is referring to.