DRAM Timing
- Enhance Data transmitting: Normal
- Enhance Addressing: Normal
- T2 Dispatch: Enabled
Clock Setting Fine Delay
Ch1 Clock Crossing Setting: More Relaxed
- DIMM 1 Clock fine delay: Current
- DIMM 2 Clock fine delay: Current
- Ch 1 Command fine delay: Current
- Ch 1 Control fine delay: Current
Ch2 Clock Crossing Setting: More Relaxed
- DIMM 3 Clock fine delay: Current
- DIMM 4 Clock fine delay: Current
- Ch 2 Command fine delay: Current
- Ch 2 Control fine delay: Current
Ch1Ch2 CommonClock Setting: More Relaxed
Ch1 RDCAS GNT-Chip Delay: Auto
Ch1 WRCAS GNT-Chip Delay: Auto
Ch1 Command to CS Delay: Auto
Ch2 RDCAS GNT-Chip Delay: Auto
Ch2 WRCAS GNT-Chip Delay: Auto
Ch2 Command to CS Delay: Auto (where cpuz sees 1T or 2T SETTING)
CAS Latency Time (tCL):5
RAS# to CAS# Delay (tRCD):5
RAS# Precharge (tRP):5
Precharge Delay (tRAS):15
All Precharge to Act: 6
REF to ACT Delay (tRFC): 54
Performance LVL (Read Delay) (tRD): 8
Read delay phase adjust: Enter
Ch1 Read delay phase (4~0)
- Channel 1 Phase 0 Pull-In: Enabled
- Channel 1 Phase 1 Pull-In: Enabled
- Channel 1 Phase 2 Pull-In: Enabled
- Channel 1 Phase 3 Pull-In: Enabled
- Channel 1 Phase 4 Pull-In: Enabled
Ch2 Read delay phase (4~0)
- Channel 2 Phase 0 Pull-In: Enabled
- Channel 2 Phase 1 Pull-In: Auto
- Channel 2 Phase 2 Pull-In: Enabled
- Channel 2 Phase 3 Pull-In: Enabled
- Channel 2 Phase 4 Pull-In: Enabled
MCH ODT Latency: AUTO
Write to PRE Delay (tWR): 14
Rank Write to Read (tWTR): 11
ACT to ACT Delay (tRRD): 3
Read to Write Delay (tRDWR): 8
Ranks Write to Write (tWRWR): 6
Ranks Read to Read (tRDRD): 6
Ranks Write to Read (tWRRD): 5
Read CAS# Precharge (tRTP): 3
ALL PRE to Refresh: 6
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