Quote Originally Posted by savantu View Post
Intel OTOH used dry at 45nm allowing maximum capital reuse from 65nm.The downside was they needed double patterning which cut FAB output ( see shortages of Penryns ; this will be solved as more FABs come online - Intel plans 4 45nm FABs ).

But it won't be easy either for AMD/IBM at 32nm.Why ? Because they will change from low-k SOI to high-k/metal bulk SOI.
I'd say it is more difficult to change the process than the tools ( since there are a few tool makers , Nikon , Canon , ASML ).Basically , the tools are the same for all , what matters is the process.

That's not entirely correct, the double patterning for Intel's 45nm will certainly take the extra time of 1 more pass, but that is not a limiting factor for why there's shortages of Penryn. The double pass is used on only 1 layer. All other layers are standard 193nm dry patterns, even 248nm for many metal layers. You're correct that they are capacity limited right now as fabs come online, but it has nothing to do with double patterning. In fact, double patterning is just as fast (or slow) as immersion litho, and quite a bit cheaper, so everyone will be subject to these timing constraints when they migrate to it.

Next, Low-K Interlayer Dialectrics and Hi-K/Metal Gate have really nothing to do with each other. In fact, BOTH will be (are) implemented in Intel's 45nm and IBM's/AMD's 32nm process. Intel definately uses Low-K dialectrics for the metal layers, it's just not trumpeted as much as the other camp. The reason you use low-k ILD's is to either mitigate cross-talk between metal interconnects or to be able to reduce interconnect feature size with the same relative cross-talk (or some combo of both). Considering that AMD actually has MORE metal layers than Intel I am curious as to how good their Low-K solution is.

High-K/Metal gate is a method to physically increase the thickness of the Transistor gate dialectric, while electrically making it thinner. Semi companies have reached the physical limit of gate oxide scaling for SiO2 (about 1nm) and will not be able to decrease it any further without significant gate leakage problems. A high-K dialetric now allows the industry to further scale down the gate stack dimensions for performance and reducing the effects of leakage and tunneling.

It is also unclear if IBM/AMD will use SOI or Bulk silicon processing when they transition to High-K/Metal gate although they will likely forgo SOI and move to Bulk since it should be "easier" and cheaper.