Official DFI LanParty UT X38-T2R(and LT) Discussion/Review/Overclock/Guide Thread

[cstkl1]

Well, I may have figured that out. Seems I could not load 3DM06 even @ stock, so I did some more looking. IDK if I installed the hotfix when I installed Vista, but I installed it tonight and 3DM06 loads and runs fine. I knew something was up when I could run 3D games but not 3DM06.

Any advice on where to tweak next?

CPU Feature Page
Thermal Management Control................Disabled
PPM (EIST) Mode...........................Disabled
Limit CPUID MaxVal........................Disabled
CIE Function..............................Disabled
Execute Disable Bit.......................Enabled
Virtualization Technology.................Enabled
Core Multi-Processing.....................Enabled

Main BIOS Page
Exist Setup Shutdown......................Mode 2
Shutdown After AC Loss....................Disabled
O. C. Fail Retry Counter..................0
CLOCK VC0 Divider.........................Auto
CPU Clock Ratio...........................9x
CPU Clock.................................400 MHz
Boot Up Clock.............................Auto
DRAM Speed................................333/800 <- DDR2-960
PCIE Clock................................100MHz
PCIE Slot Config..........................1X 1X

CPU Spread Spectrum.......................Disabled
PCIE Spread Spectrum......................Disabled
SATA Spread Spectrum......................Disabled

Voltage Setting Page 
CPU VID Control...........................1.37500V
CPU VID Special Add.......................Auto
DRAM Voltage Control......................2.23V (BIOS shows 2.2v)
SB Core/CPU PLL Voltage...................1.510V
NB Core Voltage...........................1.504V
CPU VTT Voltage...........................1.453V
VCore Droop Control.......................Enabled
Clockgen Voltage Control..................3.45V
GTL+ Buffers Strength.....................Strong
Host Slew Rate............................Weak
GTL REF Voltage Control...................Enabled
CPU GTL1/3 REF Volt.......................130
CPU GTL 0/2 REF Volt......................120
North Bridge GTL REF Volt ................100

DRAM Timing Page
Enhance Data Transmitting.................Fast
Enhance Addressing........................Fast
T2 Dispatch...............................Auto
Clock Setting Fine Delay..................Listed Below
CAS Latency Time (tCL)....................5
RAS# to CAS# Delay (tRCD).................5
RAS# Precharge (tRP)......................4
Precharge Delay (tRAS)....................12
All Precharge to Act......................5
REF to ACT Delay (tRFC)...................26
Performance Level.........................7
Read Delay Phase Adjust...................Listed Below
MCH ODT Latency...........................Auto
Write to PRE Delay (tWR)..................11
Rank Write to Read (tWTR).................11
ACT to ACT Delay (tRRD)...................3
Read to Write Delay (tRDWR)...............8
Ranks Write to Write (tWRWR)..............4
Ranks Read to Read (tRDRD)................5
Ranks Write to Read (tWRRD)...............4
Read CAS# Precharge (tRTP)................3
ALL PRE to Refresh........................5

Read Delay Phase Adjust Page
Channel 1 Phase 0 Pull-In.................Auto
Channel 1 Phase 1 Pull-In.................Auto
Channel 1 Phase 2 Pull-In.................Auto
Channel 1 Phase 3 Pull-In.................Auto
Channel 1 Phase 4 Pull-In.................Auto

Channel 2 Phase 0 Pull-In.................Auto
Channel 2 Phase 1 Pull-In.................Auto
Channel 2 Phase 2 Pull-In.................Auto
Channel 2 Phase 3 Pull-In.................Auto
Channel 2 Phase 4 Pull-In.................Auto

Clock Setting Fine Delay Page
Ch1 Clock Crossing Setting................Auto
DIMM 1 Clock fine delay...................Current 156ps
DIMM 2 Clock fine delay...................Current 534pd
DIMM 1 Control fine delay.................Current 601ps
DIMM 2 Control fine delay.................Current 356ps
Ch 1 Command fine delay...................Current 868ps

Ch2 Clock Crossing Setting................Auto
DIMM 3 Clock fine delay...................Current 156
DIMM 4 Clock fine delay...................Current 467
DIMM 3 Control fine delay.................Current 445
DIMM 4 Control fine delay.................Current 434
Ch 2 Command fine delay...................Current 868

Ch1Ch2 CommonClock Setting................Auto

Ch1 RDCAS GNT-Chip Delay..................Auto
Ch1 WRCAS GNT-Chip Delay..................Auto
Ch1 Command to CS Delay...................Auto

Ch2 RDCAS GNT-Chip Delay..................Auto
Ch2 WRCAS GNT-Chip Delay..................Auto
Ch2 Command to CS Delay...................Auto

hmm ure vtt is too high.
disable the vdroop.
reduce it to stock and leave the gtl at default.. wont make a difference at 400fsb for c2d
NB around 1.4 or less
and this is mainly ure prob on ure rams

Ranks Write to Write (tWRWR)..............4
Ranks Read to Read (tRDRD)................5
Ranks Write to Read (tWRRD)...............4

try 6 6 5

better if u try this

set ure NB to 1.356
GTL on Auto
Ram Setting all of them on AUTO except
T2 Disaptch = Disabled
and Set 5-5-5-15

Performance Level Auto .. no need to mess with it... as it will choose the lowest. and equal for both channel
and Choose the 266/something strap to get 1000mhz

should be piece of cake at 2.23v