Intel Details Nehalem uArch Improvements - 256KB L2, 8MB L3 Confirmed

[BrowncoatGR]

The 12MB L3 on a Itanium 2 Montecito has 14 cycles latency.The The L2 has 5 for Int and 7 for FP.

Core 2 has 14 cycles for L2 ; K8 has 12 for L2 ; K10 L2 is 15 , L3 is 30 to 45.

Not true for K10. L2 is 12 cycles just like K8. Also L3 latency is higher than 30.
See here http://www.digit-life.com/articles3/...ma-phenom.html

This gate thickness is about 0.15-0.2 nm thinner than either AMD or Intel at 65 nm (their reported thicknesses were 1.3 nm and 1.25 nm respectively as I recall). Translation, IBM's power 6 is a power sucker.

http://www.research.ibm.com/journal/rd/516/berridge.pdf

Just a minor correction. AMDs figures are quite old and can very well have changed since then because of CTI.

AMD CPUs don't have a FSB, how do those get overclocked?

Well AMD chips have a reference HTT clock not a PCI-E clock. If future mainstream Intel CPUs get their clock from the PCI-E bus then overclocking is going to get severly limited because increasing PCI-e clocks too much causes data corruption and stability problems for various hardware. Lets hope Intel will put the pci-e on a seperate clock domain and get CPU speed from somewhere else.
@KTE Simply amazing and very informative post. Thank you