Again we don't know, AMD's L3 cache operates at NB speeds, but this is not what kills them on latency so much as they need FIFO buffers which absorb the clocks skew.... Even with this new information, we don't have too much info on Nehalem, heck, Intel may have done similar dividing of the clock domains, in which case they will also have similar latency hits in the cache hierarchy.
It is funny to watch people talk 'Retun of 20 stage pipeline', etc etc above when that info has never been released or disclosed by Intel... people are talking like they know detailed spec, I find it amusing![]()
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