Howto disable the tlb-fix with CrystalCPU

[Raiderman]

Yes, in the same directory and tried running them as admin, no luck though. Vista x64.

I had the same error while trying to execute the file while it was still packed in the rar file. If you extract it to the same dir as crystal cpu, then right click, run as admin, everything should work perfectly.

[madfaze]

I had the same error while trying to execute the file while it was still packed in the rar file.

you were to run while it was still packed?!

[Raiderman]

LOL I know I was in a hurry

[Raiderman]

Is there a way to disable the dialogue box from popping up on startup. It would be cool to have the command window open at startup, apply the fix and then disapear.

@sam, thanks for your hard work, its much appreciated!
@KTE. thanks also

[madfaze]

LOL I know I was in a hurry

lolz! excited you mean...how was your OC?

[LIKMARK]

Is your error message "Cannot load DLL!". Can you find the Sysinfo.DLL in the same directory? I myself use x64, so should be no problem.

That's the message yes. You mean the sysinfox64.dll I presume? Yes I can find it, but I can't find a sysinfo.dll. No

[sam2008]

That's the message yes. You mean the sysinfox64.dll I presume? Yes I can find it, but I can't find a sysinfo.dll. No

No, I mean sysinfo.dll. Try redownload the CrystalCPUID, make sure sysinfo.dll is in there. Then you should be fine.

[LIKMARK]

ok, had to download the x86 version. not the x64 version. Then it worked. Gonna restart now and see
Tested winrar right away and got 1200kb/s against 240 with tlb patch enabled. Thanks

[KTE]

sam2008: Is there any way to control which cores the MSR is applied to in your app through the ini?

It's because I (and many) oc at bootup settings where 1 core will fail but the rest of 3 won't, to then change the MSR for that weak core to drop multiplier one notch and let it run at lower MHz while the other 3 run at bootup MHz. This isn't the hardest bit, but the bit I need is, when CnQ is enabled I used your app to drop to 0.850VID 800MHz on all cores, but with load, they all need to get back up to the multi's I set initially and not all the same multi (which is what they do unless I change MSR for each core separately).

So say I use 13x on first 3 cores and 12.5x multi on the last core, even with CnQ enabled, I'd want it to remain max 12.5x under load (or it'd crash).

Is there any way yet? This'll come in handy for you, test your Phenom, it will very likely have one core very weak compared to the rest.

[sam2008]

KTE: You word is my command. One way to do it is to add a core mask option in the ini file. I.E. 0b1011 stands for enabling writing to core 1, 2, and 4, but not core 3. How does that sound to you?

[KTE]

Sounds perfect, eager to test.
We use "-coremask=x" to disable a core using CPU-Z to avoid the weak core and we also tried disabling a specific core using Bus:0h Dev:24h Fct:3h Offset:BEh 0000000000000000b [core 3,2,1,0], both of them never worked as we wanted so I suppose it is similar to both methods in a way but to get something better done. A DIY replacement for BIOS multi.

[sam2008]

KTE: I have uploaded the ver1.02 at POST #90. Try to keep all the updates in one post so that it won't be scatter all around. You can download from there. Basically added support for core masking in the INI file. Let me know how it worked out for you .

Now you can use the COREMASK to specify which core you want the MSR value to be written. It is 4-bit binary value. The lowest bit is core 1, second bit is core 2, third bit is core 3, and fourth bit is core 4. When a bit is set to 1, MSR for that core will be written. If a bit is set to zero, the program will skip the MSR for that core. For example, 0b1011 means core 1, 2, and 4 will be written, and core 3 will be skipped. If COREMASK is set to 0b1111, then the selected MSR for all four cores will be written. If COREMASK is set to 0b0000, then selected MSR won't be written to any of the cores. Changing the COREMASK value accordingly. It is set at 0b1111 by default (all 4 core enabled).

[sam2008]

I usually like something to indicate that all things are working fine. Otherwise, the console window will just flash and disappear not really know what's going on. That's why I deliberately added the message box. But as you wish, I updated the program, now you can choose to disable the popup message box by adding the -nopop argument at the end of the program. If no argument is provided, the box will popup by default. Go to RebelsHeavenForum to download the TLB ver1.03. In Vista, you have to add the argument -nopop thru the taskscheduler. Hope it works for you.

Is there a way to disable the dialogue box from popping up on startup. It would be cool to have the command window open at startup, apply the fix and then disapear.

@sam, thanks for your hard work, its much appreciated!
@KTE. thanks also

[KTE]

Sam2008: thank you!

Works perfect. However quick qs: does coremask value override the mask_high/mask_low parameter?

What I mean is if I set:

index=0xc0010070
high=0x00000000
low=0x5000340A
mask_low=0xFFFFFFFF
mask_high=0xFFFFFFFF
coremask=0b0111

Will it write 0x5000340A to core4 or skip it reading the mask_low=0xF?

Could you not use mask_low/mask_high values 0/1/2/3/4/5/6/7/8/9/A/B/C/D/E/F to do the same?
i.e. using the above, me wanting to write to core 3 (340A) only=>

index=0xc0010070
high=0x00000000
low=0x5000340A
mask_low=0xFFFFF777 (mask 0111b)
mask_high=0xFFFFFFFF

Would this work?

TBH only now has Phenom really become insanely tweakable and fun to play with.

[mibo]

I updated my RW-Everything batch file and now it's using AND to clear only the needed bits and not changing the rest of the msr register.
I used the new version 0.29 of RW-Everything.

>cpu 1
read register to LocalD:LocalA
>rdmsr 0xc0010015
set bit#4 to zero
>LocalA = AND LocalA 0xfffffff7
write back
>wrmsr 0xc0010015 LocalD LocalA
read register to LocalD:LocalA
>rdmsr 0xc0011023
set bit#2 to zero
>LocalA = AND LocalA 0xfffffffd
write back
>wrmsr 0xc0011023 LocalD LocalA

>cpu 2
read register to LocalD:LocalA
>rdmsr 0xc0010015
set bit#4 to zero
>LocalA = AND LocalA 0xfffffff7
write back
>wrmsr 0xc0010015 LocalD LocalA
read register to LocalD:LocalA
>rdmsr 0xc0011023
set bit#2 to zero
>LocalA = AND LocalA 0xfffffffd
write back
>wrmsr 0xc0011023 LocalD LocalA

>cpu 3
read register to LocalD:LocalA
>rdmsr 0xc0010015
set bit#4 to zero
>LocalA = AND LocalA 0xfffffff7
write back
>wrmsr 0xc0010015 LocalD LocalA
read register to LocalD:LocalA
>rdmsr 0xc0011023
set bit#2 to zero
>LocalA = AND LocalA 0xfffffffd
write back
>wrmsr 0xc0011023 LocalD LocalA

>cpu 4
read register to LocalD:LocalA
>rdmsr 0xc0010015
set bit#4 to zero
>LocalA = AND LocalA 0xfffffff7
write back
>wrmsr 0xc0010015 LocalD LocalA
read register to LocalD:LocalA
>rdmsr 0xc0011023
set bit#2 to zero
>LocalA = AND LocalA 0xfffffffd
write back
>wrmsr 0xc0011023 LocalD LocalA

>rwexit

[sam2008]

Coremask determines which core's MSR you want to write. Mask_low, and Mask_high determines which bit in the MSR you want to write. Coremask has a higher priority. If you set coremaks=binary 0111, then it will skip any writing operation to core 4.

If you set
index=0xc0010070
high=0x00000000
low=0x5000340A
mask_low=0xFFFFFFFF
mask_high=0xFFFFFFFF
coremask=0b0111

You will skip core 4. Nothing will done to core 4. Also since you set the mask_low and mask_high=0xffffffff, so you mask all bits in that MSRs in the other 3 cores. So no change will be made to the MSRs in core 1,2,3 (or actually, it will read the original values in the MSRs in core 1,2,3, and write the original value back in). If you set mask_low and mask_high=0x00000000, then MSRs in core 1,2,3 will be written with 0x5000340A. Still nothing will be done to core 4 because of coremask=0111(b) told the program to skip it.

The mask_high and mask_low are only useful if you want certain bits in the MSR not to be change. If you want to directly write the specified value into the MSRs, you should set them to 0x00000000.

For example, if the original low value of a MSR is 0x10000203, and you want change the its 1-4 bits to 9, and 60-64 bits to 4, but do not want to touch the bits 5-59 and want to keep them the way they are originally. Then you can use the mask_low=0x0FFFFFF0, and write the low=0x4BBBBBB9 (B represents a non-care value since it will be masked off) into that MSR. The final value of MSR after the operation will be 0x40000209.

If you just want to write a specified value directly into MSRs, then set the Mask_high, mask_low=0x0.

Sam2008: thank you!

Works perfect. However quick qs: does coremask value override the mask_high/mask_low parameter?

What I mean is if I set:

index=0xc0010070
high=0x00000000
low=0x5000340A
mask_low=0xFFFFFFFF
mask_high=0xFFFFFFFF
coremask=0b0111

Will it write 0x5000340A to core4 or skip it reading the mask_low=0xF?

Could you not use mask_low/mask_high values 0/1/2/3/4/5/6/7/8/9/A/B/C/D/E/F to do the same?
i.e. using the above, me wanting to write to core 3 (340A) only=>

index=0xc0010070
high=0x00000000
low=0x5000340A
mask_low=0xFFFFF777 (mask 0111b)
mask_high=0xFFFFFFFF

Would this work?

TBH only now has Phenom really become insanely tweakable and fun to play with.

[sam2008]

Yeh, RW-Everything is good tool. But it uses a unsigned driver. So in Vista, it will cause my Vista go into a so called "TEST MODE" (driver signing forced to disable) with watermarks over the desktop.

I updated my RW-Everything batch file and now it's using AND to clear only the needed bits and not changing the rest of the msr register.
I used the new version 0.29 of RW-Everything.

[Raiderman]

I usually like something to indicate that all things are working fine. Otherwise, the console window will just flash and disappear not really know what's going on. That's why I deliberately added the message box. But as you wish, I updated the program, now you can choose to disable the popup message box by adding the -nopop argument at the end of the program. If no argument is provided, the box will popup by default. Go to RebelsHeavenForum to download the TLB ver1.03. In Vista, you have to add the argument -nopop thru the taskscheduler. Hope it works for you.

WOW! You Rock! Usually I only get it my way at Burger King

[KTE]

Yeah I understand that much and have been doing it but was thinking if Fh = 1111b, so you chose to mask the bit, but 0h = 0000b so you chose to not mask those, then maybe (I was hoping) we could use.. never mind

It won't work, since bits don't stand for each core.

[sam2008]

@KTE, I know it is a bit confusing, using 1 stand for disabling the MSR bit, but also use 1 for enabling cores. That's all because MSR masking was originally based on the convention set by justapost .

So does it work out the way you wanted now? Crank up the multiplier for 1,2 and 4 and lower the multi for defective core 3? Just wondering can't you adjust that in AOD? I guess AOD probably won't let you save the settings.

Hmm tht ini file approach looks nice and easy. Best would be if you can define a mask and a value for a variable number of MSR registers.

Example:
Code:

[MSR]
C0010015_value=0x00000008
C0010015_mask=0x00000008
[MSR0]
C0010064_value=0x2C0020A0
C0010064_mask=0x00ff0000

All stuff in MSR would be applied to all cores stuff in MSR0-MSR3 whould be core specific.
App must read the MSR register, apply the mask and add add the value.

[justapost]

I understand the question like that:

If you apply an value to an MSR on multiple cores, do you perform the masking for each core or do you use the result from the first core for the other cores?

BTW I like the result a lot better than my proposal. I guess coremask might also work on multi socket machines.

[sam2008]

Masking is performed separately for each core's MSR's original value since I realized in certain circumstances the bit values for MSR for different cores might be different.

I understand the question like that:
If you apply an value to an MSR on multiple cores, do you perform the masking for each core or do you use the result from the first core for the other cores?

[sam2008]

@KTE, any exciting results on separately adjusted multipliers for each core ?

[KTE]

Sorry, Phenom=no boot for many hours yet. It happens randomly when I reset BIOS on my Phenom as it did on my 1st one.

So I've not checked. I know 2700x3/2600x1 is fully stable though, not tried more yet. 2665 will also be stable on core3 and 2754 is max I know is stable with core 0,1,2 so I'll give it a try for more 100% stability. Around 222x12.5 3 cores and 222x12 on last core next stop.

[Torpedo]

Thank U sam2008, great job!