M3A overclocking

[tictac]

Polygon from RebelsHaven was so kind to mod the 601 Bios in a way that the Lan-Boot field can be used to disable the fix (enabled the tlb).



I did not yet test it, cuz i'm running few stability test's with phenom on the m2a-vm atm.

In case you want to try it I uploaded the bios to rapidshare here.

Woa... !!! lucky you...
new bios from the master

[RebelsHaven]

You are too kind, my friend! Without your work on the A64 ROM Patcher, we would be nowhere today

Just a warning:

The BIOS is UNTESTED and the BIOS chip is soldered in. If the BIOS is corrupt, RMA may be the only answer!

Edit: I will have the board in a few days and will test the mod BIOS

[justapost]

You are too kind, my friend! Without your work on the A64 ROM Patcher, we would be nowhere today

Just a warning:

The BIOS is UNTESTED and the BIOS chip is soldered in. If the BIOS is corrupt, RMA may be the only answer!

Edit: I will have the board in a few days and will test the mod BIOS

Polygon, tried your modded bios. Flashed it from USB from within the bios without problems.
System boots without problems. But the mod does not work. I get the same everest results with Lan-Boot en/dis-abled.
Also Crystalcpu still has the tlb-disabled flag set (checked only the firt core).

[RebelsHaven]

Hmmm... may be a little confusion here... When you say it's "set", you mean it's a "1" correct? I'm already writing a 1b to the 4th bit of the MSRC001_0015 register. If the BIOS already has written a 1b, of course, there will be no change. Do you want a 0b written to the 4th bit or a 1b? I'm writing a 1b. Very easy to change. Here's a BIOS with it the other way:

http://www.lejabeach.com/ASUS/M3A/601RHCF3.zip

This BIOS is UNTESTED and the BIOS chip is soldered in. If the BIOS is corrupt, RMA may be the only answer! Be careful!

[justapost]

Hmmm... may be a little confusion here... When you say it's "set", you mean it's a "1" correct? I'm already writing a 1b to the 4th bit of the MSRC001_0015 register. If the BIOS already has written a 1b, of course, there will be no change. Do you want a 0b written to the 4th bit or a 1b? I'm writing a 1b. Very easy to change. Here's a BIOS with it the other way:

http://www.lejabeach.com/ASUS/M3A/601RHCF3.zip

This BIOS is UNTESTED and the BIOS chip is soldered in. If the BIOS is corrupt, RMA may be the only answer! Be careful!

Hi Polygon,

Yepp the bit must be unset, that reenables the TLB.
Tried the new bios and it works. But you remove that bit only on core0. It should be done on all four cores, but that may cause problems if cores are disabled via the bios.

Anyway, thank you for your effort, having an option for the tlb-fix is a comfortable thing.

[RebelsHaven]

Hello!
Interesting. That same fix sets or unsets all 4 cores in the Biostar TA770 board. There are several MSR's that there is only 1 per CPU. Isn't the HWCR one of the MSR's that are 1 per CPU and not in every core?

[justapost]

Hello!
Interesting. That same fix sets or unsets all 4 cores in the Biostar TA770 board. There are several MSR's that there is only 1 per CPU. Isn't the HWCR one of the MSR's that are 1 per CPU and not in every core?

I ran RightMark multi-threaded mem test and it gave me the same bandwidth on all cores.
Guess you are right about the HWCR. But it's odd that CrystalCPU still reads 8h for cpu's 1-3 but 0h for cpu0. If it's the same register for all cores it should read the same value, or is only the core0 register used in a per cpu case?

[RebelsHaven]

I honestly don't know if it's 1 per CPU or 1 per core. I assumed 1 per CPU because setting it on core0 shows it changed on the other 3 in the Biostar board. I'm not sure how to address the other cores from the BIOS anyhow.

The BKDG for the Phenom is very tough to read and many things are not explained, where in the BKDG for AM2 and A64, it was very clear...

But, I'm glad it seems to be working correctly... Thanks for testing it!

[justapost]

I honestly don't know if it's 1 per CPU or 1 per core. I assumed 1 per CPU because setting it on core0 shows it changed on the other 3 in the Biostar board. I'm not sure how to address the other cores from the BIOS anyhow.

Only if you change it from within the bios or does it also behave like this if you change that register with crystalcpu?

The BKDG for the Phenom is very tough to read and many things are not explained, where in the BKDG for AM2 and A64, it was very clear...

Dunno the guide for A64/AM2 but the BKDG really is tough, hope a new revision will add abit extra background information.

But, I'm glad it seems to be working correctly... Thanks for testing it!

Glad I could help.

BTW: A you aware of an 770 chipset mobo, whom is able to apply more than 1,25V to a k10 cpu?

[RebelsHaven]

Writing the Biostar from the BIOS, changes all 4 cores for the TBL-Fix only. Writing to the other patch you discovered(MSRC001_1023), does not write to all 4 cores. Also writing to P-State0(MSRC001_0064) only writes to P-State0 for core0... I can't figure out how to write to all 4 cores!

Writing to MSRC0010015 with CrystalCPUID only changes 1 at a time...

I've had the Biostar TA770-A2+ running with 1.5Vcore for my Phenom....

I'm getting the ASUS M3A and if it needs a Vcore mod, I can do that, no problem. Is that Vcore limited?

[justapost]

Writing the Biostar from the BIOS, changes all 4 cores for the TBL-Fix only. Writing to the other patch you discovered(MSRC001_1023), does not write to all 4 cores. Also writing to P-State0(MSRC001_0064) only writes to P-State0 for core0... I can't figure out how to write to all 4 cores!

I took a look in the linux kernel sources. The function whom is affected by the linux-tlb patch gets called for core0 only. I'll inspect the msr registers in linux now.

I've had the Biostar TA770-A2+ running with 1.5Vcore for my Phenom....

I'm getting the ASUS M3A and if it needs a Vcore mod, I can do that, no problem. Is that Vcore limited?

My theory for the M3A is that those fields labled prozessor and nb voltages are the cpu/nb vid's. I can select more than 1,25V but the internal decimal places get mapped to the 1,2V-1,25V range.
AMD Power Monitor reports exact the values i set in the bios, cpu-z's vcore is pretty close 1,264V max if I select 1,25V in the bios.
You have an BE or an 9500/9600 as those have upward locked vid's?

[RebelsHaven]

I have a 9500. I'll have to measure the Vcore at 1.50V to see what it is...

[justapost]

I took a look in the linux kernel sources. The function whom is affected by the linux-tlb patch gets called for core0 only. I'll inspect the msr registers in linux now.

The registers all showed the modified value. The patch adds a note to the kernel log if it changes the msr registers.

Here is the excerpt of the log for cores 1-3, core 0 get's called on an earlier stage.

SMP alternatives: switching to SMP code
Booting processor 1/4 APIC 0x1
Initializing CPU#1
Calibrating delay using timer specific routine.. 4400.40 BogoMIPS (lpj=8800810)
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 512K (64 bytes/line)
CPU 1/1 -> Node 0
AMD erratum 298 bios fix disabled
CPU: Physical Processor ID: 0
CPU: Processor Core ID: 1
AMD Phenom(tm) 9500 Quad-Core Processor stepping 02
SMP alternatives: switching to SMP code
Booting processor 2/4 APIC 0x2
Initializing CPU#2
Calibrating delay using timer specific routine.. 4400.39 BogoMIPS (lpj=8800788)
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 512K (64 bytes/line)
CPU 2/2 -> Node 0
AMD erratum 298 bios fix disabled
CPU: Physical Processor ID: 0
CPU: Processor Core ID: 2
AMD Phenom(tm) 9500 Quad-Core Processor stepping 02
SMP alternatives: switching to SMP code
Booting processor 3/4 APIC 0x3
Initializing CPU#3
Calibrating delay using timer specific routine.. 4400.45 BogoMIPS (lpj=8800903)
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 512K (64 bytes/line)
CPU 3/3 -> Node 0
AMD erratum 298 bios fix disabled
CPU: Physical Processor ID: 0
CPU: Processor Core ID: 3
AMD Phenom(tm) 9500 Quad-Core Processor stepping 02
Brought up 4 CPUs

You can see the patch get's applied for each core in opposite to my first adoption.
Aint there no simple assembler commando to select the cpu? Don't know much about bios coding, I assumed you change the jump target in the gui part of the bios to a place where you have stored your modified machine code.

[KTE]

VID decides VCore on AM2+.

Achim: Check MSR C001_0064 and post this back please:




Tell me what you set in BIOS for CPU voltages and what CPUZ reads too.

[RebelsHaven]

Aint there no simple assembler commando to select the cpu? Don't know much about bios coding, I assumed you change the jump target in the gui part of the bios to a place where you have stored your modified machine code.

In x86 assembly, there is no directive that I know of to select a different core. I'm afraid it might have to be performed with a call to a seperate module. I really don't know... But I think the other 3 cores may get addressed by APIC directives...

To do the mod I did, I wrote a substitute PCI LAN Boot ROM and replaced the original. The new ROM writes to the MSR when it's executed and that is when the LAN Boot is enabled during POST....

[justapost]

VID decides VCore on AM2+.

Achim: Check MSR C001_0064 and post this back please:




Tell me what you set in BIOS for CPU voltages and what CPUZ reads too.

Aight, here we go.

PState-0 Status

COFVID Status


Results in 11010b for the vid equals 1,225V That's what I set in the bios as prozessor voltage.
CPU-Z 1,216V/idle 1,232V/load.

How much higher can vcore be choosen than the vid on your mobo?

[justapost]

In x86 assembly, there is no directive that I know of to select a different core. I'm afraid it might have to be performed with a call to a seperate module. I really don't know...

Last time I wrote assemble code was more than twenty years ago on an atari st, so i'm not up to date here. I'll swap disc again and try to find out how it is done in the linux kernel.

To do the mod I did, I wrote a substitute PCI LAN Boot ROM and replaced the original. The new ROM writes to the MSR when it's executed and that is when the LAN Boot is enabled during POST....

That sounds like a pretty save way to mod the bios. Is this A64 Rom Patcher public available? Googled for it but the only related result was your post here.

[KTE]

Aight, here we go.

PState-0 Status

COFVID Status


Results in 11010b for the vid equals 1,225V That's what I set in the bios as prozessor voltage.
CPU-Z 1,216V/idle 1,232V/load.

Those are stock VID/VCore on 9500, yep. VID is locked on 9500/9600. Max voltage on 1.25VID is around 1.488V on AM2+ CPU.

What happens if you change the processor voltage in BIOS, do those bit values change?

How much higher can vcore be choosen than the vid on your mobo?

See above. Differs for each VID for unlocked version though.

[RebelsHaven]

Last time I wrote assemble code was more than twenty years ago on an atari st, so i'm not up to date here. I'll swap disc again and try to find out how it is done in the linux kernel.

Same here. Took a year to get back into it, but it hasn't changed at all!

That sounds like a pretty save way to mod the bios. Is this A64 Rom Patcher public available? Googled for it but the only related result was your post here.

Visit:
The Rebels Haven BIOS Workshop

[justapost]

Those are stock VID/VCore on 9500, yep. VID is locked on 9500/9600. Max voltage on 1.25VID is around 1.488V on AM2+ CPU.

That correlates with my max stable vcore on the m2a-vm. On that mobo the cpu-vid (AMD PM reporting) stays at 1,25V and i can change the vcore. Not stable beyond 1,475V.

What happens if you change the processor voltage in BIOS, do those bit values change?

Tried it with 1,25V in the bios. 34xxh is 30xxh now. -> 11000b -> 1,25V.

Same here. Took a year to get back into it, but it hasn't changed at all!

Visit:
The Rebels Haven BIOS Workshop

Thanks, did not expect that much info.

Tried to find how linux modifies core related msr info. Found a few wrapper functions for reading and writing to msr registers. There are smp versions of this functions available whom have a core number variable. But those versions are just wrappers to the single core versions and the core number variable is not used.
The core selection must be hidden somewhere else.

[RebelsHaven]

Thanks, did not expect that much info.

Yes, there is a lot to it...

Vcore check:
Biostar TA770 A2+
Set Vcore: +.225V above default.
BIOS Reads: 1.47V
DMM Reads: 1.493V

[jpierce555]

Hey guys, I finally got a response from Asus, they said that I should try the 601 bios. I am assuming that means they think the voltage issue is fixed, one of you should drop them an email again to let them no it did not.

[justapost]

Yes, there is a lot to it...

Vcore check:
Biostar TA770 A2+
Set Vcore: +.225V above default.
BIOS Reads: 1.47V
DMM Reads: 1.493V

Thank you that sorts out my fear that it's an common chipset issue.

Made my way thru the linux source and found this function. She's used to call the cpu initalisation function whom applies the tlb-fix related stuff.

arch/x86/kernel/smp_64.c line 329

/*
 * this function sends a 'generic call function' IPI to all other CPU
 * of the system defined in the mask.
 */

static int
__smp_call_function_mask(cpumask_t mask,
			 void (*func)(void *), void *info,
			 int wait)
{
	struct call_data_struct data;
	cpumask_t allbutself;
	int cpus;

	allbutself = cpu_online_map;
	cpu_clear(smp_processor_id(), allbutself);

	cpus_and(mask, mask, allbutself);
	cpus = cpus_weight(mask);

	if (!cpus)
		return 0;

	data.func = func;
	data.info = info;
	atomic_set(&data.started, 0);
	data.wait = wait;
	if (wait)
		atomic_set(&data.finished, 0);

	call_data = &data;
	wmb();

	/* Send a message to other CPUs */
	if (cpus_equal(mask, allbutself))
		send_IPI_allbutself(CALL_FUNCTION_VECTOR);
	else
		send_IPI_mask(mask, CALL_FUNCTION_VECTOR);

	/* Wait for response */
	while (atomic_read(&data.started) != cpus)
		cpu_relax();

	if (!wait)
		return 0;

	while (atomic_read(&data.finished) != cpus)
		cpu_relax();

	return 0;
}

Seems it's done true IPI (Inter Prozessor Interrupts).

The involved functions seem to solve that true APIC register modification.
APIC inline functions are defined in include/asm/apic.h.

[justapost]

Hey guys, I finally got a response from Asus, they said that I should try the 601 bios. I am assuming that means they think the voltage issue is fixed, one of you should drop them an email again to let them no it did not.

Hmm I already wrote an email to that asus engineer whom sent me the 501 bios, about that issue. Guess he understood my english as good as I understood his chinese.
How far did you get with your GB mobo jpierce555? I ordered the sapphire clone of the dfi mobo today btw.

[RebelsHaven]

OK, thanks! Inter-Processor Interrupts was one of my suspicions...