Quote Originally Posted by Aerosupra View Post
I have mixed feelings ...
I have OCZ XTC SLI EPP 8500C5 2x1GB and that thing wont boot on any 300/X divider .. grr
rev.A China board with 2008/01/11 (111) official bios

I had quite success at 266/X divides (specifically 266/800) = 600mhz 5-5-5 trd 6 @ 2,23V and a Q6600 1,38V and 3600MHz,
I want to switch to 8X divider, high FSB but dont want to go crazy on the volts

Any suggestions?
Perhaps you can use some of these settings:

450x8 DDR2-1080 5-5-5-15:


Settings:

Code:
CPU Feature
- Thermal Management Control: Enabled
- PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Execute Disable Bit: Enabled
- Virtualization Technology: Enabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
Shutdown after AC Loss: Disabled
CLOCK VC0 divider: AUTO
CPU Clock Ratio Unlock: Enabled
CPU Clock Ratio: 8
- Target CPU Clock:
CPU Clock: 450
Boot Up Clock:
DRAM Speed: 333/800
- Target DRAM Speed:
PCIE Clock: 100mhz
PCIE Slot Config: 1X 1X

CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled

Voltage Settings
CPU VID Control: 1.3875V
CPU VID Special Add: Auto
DRAM Voltage Control: 2.230V
SB Core/CPU PLL Voltage: 1.510V
NB Core Voltage: 1.504V
CPU VTT Voltage: 1.211V
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45V
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Disable
x CPU GTL1/3 REF Volt: 110
x CPU GTL 0/2 REF Volt: 110
x North Bridge GTL REF Volt: 110

DRAM Timing
- Enhance Data transmitting: Fast
- Enhance Addressing: Fast
- T2 Dispatch: Enabled

Clock Setting Fine Delay
Ch1 Clock Crossing Setting: More Relaxed
- DIMM 1 Clock fine delay: Current
- DIMM 2 Clock fine delay: Current
- Ch 1 Command fine delay: Current
- Ch 1 Control fine delay: Current


Ch2 Clock Crossing Setting: More Relaxed
- DIMM 3 Clock fine delay: Current
- DIMM 4 Clock fine delay: Current
- Ch 2 Command fine delay: Current
- Ch 2 Control fine delay: Current

Ch1Ch2 CommonClock Setting: More Relaxed

Ch1 RDCAS GNT-Chip Delay: Auto
Ch1 WRCAS GNT-Chip Delay: Auto
Ch1 Command to CS Delay: Auto

Ch2 RDCAS GNT-Chip Delay: Auto
Ch2 WRCAS GNT-Chip Delay: Auto
Ch2 Command to CS Delay: Auto (where cpuz sees 1T or 2T SETTING)

CAS Latency Time (tCL):5
RAS# to CAS# Delay (tRCD):5
RAS# Precharge (tRP):5
Precharge Delay (tRAS):15
All Precharge to Act: 4
REF to ACT Delay (tRFC): 42
Performance LVL (Read Delay) (tRD): 8

Read delay phase adjust: Enter

Ch1 Read delay phase (4~0)
- Channel 1 Phase 0 Pull-In: Enabled
- Channel 1 Phase 1 Pull-In: Enabled
- Channel 1 Phase 2 Pull-In: Enabled
- Channel 1 Phase 3 Pull-In: Enabled
- Channel 1 Phase 4 Pull-In: Enabled

Ch2 Read delay phase (4~0)
- Channel 2 Phase 0 Pull-In: Enabled
- Channel 2 Phase 1 Pull-In: Auto
- Channel 2 Phase 2 Pull-In: Enabled
- Channel 2 Phase 3 Pull-In: Enabled
- Channel 2 Phase 4 Pull-In: Enabled

MCH ODT Latency: 2
Write to PRE Delay (tWR): 14
Rank Write to Read (tWTR): 11
ACT to ACT Delay (tRRD): 3
Read to Write Delay (tRDWR): 8
Ranks Write to Write (tWRWR): AUTO
Ranks Read to Read (tRDRD): AUTO
Ranks Write to Read (tWRRD): AUTO
Read CAS# Precharge (tRTP): 3
ALL PRE to Refresh: 4