Some QX9650 results with MSI P35D3 Platinum, STT DDR3 1600 and 2-Stage Cascade

[before]

I've got tons of things to do; so I didn't had the time to bench more on this board. BTW; I've added a second solid aluminium capacitor to the vFSB area; and made some investigations on MCHBAR coding.

So; the memory bandwidth/latency is definitely better while booting at 399FSB with FSBSEL jumpers set to 333 strap. Of course, this setting also adds more stress on the MCH, and obviously varies with CPU multipliers. That's odd indeed.

In fact, stability is quite good with 10x multiplier, but becomes bad with 13x multiplier using the exact same bios settings... Why?

I've made registers dumps to perform comparisons. Here are the differences (quite a lot for only a multiplier difference )

399FSB

MCH x13 x10
 
140  FB  FD
141  20  60 
142  1F  1E
148  61  E1
149  59  38
184  01  61
185  9D  15
188  F4  E6
189  D1  11
198  00  12
1A8  01  02
24A  C6  C7
36E  4C  C9
36F  C6  C4
52C  12  00
52D  33  21
530  65  43
531  88  66
A0C  76  77
A14  07  08
BC1  49  47
BC3  49  47
BD8  17  1B
BDA  17  1B

I'll not come to details, but the first one which shines on my eyes is offset MCH+24A (FED1424Ah). Just check line starting with 24A. In fact, as you can see offset 24A = C6 with CPU multiplier 13x, and = C7 with CPU multiplier 10x. What does that mean?

So, let me tell you. AFAIK this particular offset is where the CAS Latency (tCL) timing is hard-codded for memory Channel #0. It's a Read/Only 8bits value which requires electrical reboot to be changed. Basically, C0 = tCL1, C1 = tCL2, C2 = tCL3, etc. to C6 = tCL7 and C7 = tCL8. So, as can be seen tCL for channel #0 is 8 while booting at 399FSBx10 but 7 while booting at 399FSBx13. That's odd; knowing that I set tCL to 7 in the bios...

Then, I've tried to boot at 399FSBx13 with tCL set to 8 in the bios; and the system became stable 24A offset was correctly set to C7, just like while booting at 399FSBx10 with tCL set to 7 in the bios.

Guess there's a matter of bios coding here.

BTW dunno why, but LargeSystemCache (LSC) = 1 causes unstability again. The memory controller might be out of breath. What's interesting to note is that Spi32M can pass successfully with multiplier 13x and LSC=1 if I don't boot at 399FSB. It looks like something related to MCH data transfer limitation. I'll try with more Vmch; but I don't really like it. Actual tests were performed with 1.75Vmch (DMM).