dino i kinda disproved the high htt theory on manta......350 x 4 multi.......and 300 x 5 multi..........
heatware chew*
I've got no strings to hold me down.
To make me fret, or make me frown.
I had strings but now I'm free.
There are no strings on me
I know, remember I started the thread on thembut if we compare a BH chip not known to coldbug to a non BH chip............I bet saaya could figure it out....
heatware chew*
I've got no strings to hold me down.
To make me fret, or make me frown.
I had strings but now I'm free.
There are no strings on me
IDK about that chips design and material selection because I haven't studied it, never needed to, so I can't speak for that and each IC is very different despite it using the same design process. However SOI isn't broken in itself, but it does have material and implementational limitations with the current properties of the chemicals used in K10. They can enhance these properties and get far lower current leakage in the "on" and "off" states, higher drive current and better transistor performance throughout, which will give you better MHz at lower power/temps/volts idle and load. One of these methods is to employ a relatively thin high-k dialectric/metal gate CMOS which is exactly what they've been working on with IBM and for the above specified reason.
There's a two things:
a) a design/material frequency and current limit
b) something which causes coldbugs
The first you can't address, only AMD can.
The second you maybe can address.. if you knew what it was.(hence the thread)
And yeah saaya, what you said is true. As it gets colder, there is much less resistance and more voltage actually gets to the cores, which also affects current leakage as it decreases drastically and more is then provided to the cores. There is a massive difference with the amount of current leakage in cold/hot temps, like 40x at 50C compared to 0C, if not more.
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