Q6600 @ 450x8. Good 24/7 voltages. Nothing stressed or pushed. Memory can be run faster or with tighter timings at the expense of increased voltages.

Two screenshots of Prime, one running and one stopped. Only way to show the 8x multiplier as C1E is enabled.











Code:
CPU Feature Page
Thermal Management Control................Enabled
PPM (EIST) Mode...........................Enabled
Limit CPUID MaxVal........................Disabled
CIE Function..............................Auto
Execute Disable Bit.......................Enabled
Virtualization Technology.................Enabled
Core Multi-Processing.....................Enabled

Main BIOS Page
Exist Setup Shutdown......................Mode 2
Shutdown After AC Loss....................Disabled
O. C. Fail Retry Counter..................0
CLOCK VC0 Divider.........................Auto
CPU Clock Ratio...........................8x
CPU Clock.................................450 MHz
Boot Up Clock.............................Auto
DRAM Speed................................333/800
PCIE Clock................................100MHz
PCIE Slot Config..........................1X 1X

CPU Spread Spectrum.......................Disabled
PCIE Spread Spectrum......................Disabled
SATA Spread Spectrum......................Disabled

Voltage Setting Page 
CPU VID Control...........................1.37500V
CPU VID Special Add.......................Auto
DRAM Voltage Control......................2.190V
SB Core/CPU PLL Voltage...................1.510V
NB Core Voltage...........................1.504V
CPU VTT Voltage...........................1.327V
VCore Droop Control.......................Enabled
Clockgen Voltage Control..................3.45V
GTL+ Buffers Strength.....................Strong
Host Slew Rate............................Weak
GTL REF Voltage Control...................Disabled
CPU GTL1/3 REF Volt.......................110
CPU GTL 0/2 REF Volt......................110
North Bridge GTL REF Volt ................110

DRAM Timing Page
Enhance Data Transmitting.................Fast
Enhance Addressing........................Fast
T2 Dispatch...............................Auto
Clock Setting Fine Delay..................Listed Below
CAS Latency Time (tCL)....................5
RAS# to CAS# Delay (tRCD).................5
RAS# Precharge (tRP)......................4
Precharge Delay (tRAS)....................12
All Precharge to Act......................5
REF to ACT Delay (tRFC)...................26
Performance Level.........................8
Read Delay Phase Adjust...................Listed Below
MCH ODT Latency...........................2
Write to PRE Delay (tWR)..................14
Rank Write to Read (tWTR).................11
ACT to ACT Delay (tRRD)...................3
Read to Write Delay (tRDWR)...............8
Ranks Write to Write (tWRWR)..............4
Ranks Read to Read (tRDRD)................5
Ranks Write to Read (tWRRD)...............4
Read CAS# Precharge (tRTP)................3
ALL PRE to Refresh........................5

Read Delay Phase Adjust Page
Channel 1 Phase 0 Pull-In.................Enabled
Channel 1 Phase 1 Pull-In.................Enabled
Channel 1 Phase 2 Pull-In.................Enabled
Channel 1 Phase 3 Pull-In.................Enabled
Channel 1 Phase 4 Pull-In.................Enabled

Channel 2 Phase 0 Pull-In.................Enabled
Channel 2 Phase 1 Pull-In.................Auto
Channel 2 Phase 2 Pull-In.................Enabled
Channel 2 Phase 3 Pull-In.................Enabled
Channel 2 Phase 4 Pull-In.................Enabled

Clock Setting Fine Delay Page
Ch1 Clock Crossing Setting................More Aggressive
DIMM 1 Clock fine delay...................Current 67ps
DIMM 2 Clock fine delay...................Current 445pd
DIMM 1 Control fine delay.................Current 512ps
DIMM 2 Control fine delay.................Current 267ps
Ch 1 Command fine delay...................Current 779ps

Ch2 Clock Crossing Setting................More Aggressive
DIMM 3 Clock fine delay...................Current 67
DIMM 4 Clock fine delay...................Current 370
DIMM 3 Control fine delay.................Current 356
DIMM 4 Control fine delay.................Current 345
Ch 2 Command fine delay...................Current 779

Ch1Ch2 CommonClock Setting................More Aggressive

Ch1 RDCAS GNT-Chip Delay..................Auto
Ch1 WRCAS GNT-Chip Delay..................Auto
Ch1 Command to CS Delay...................Auto

Ch2 RDCAS GNT-Chip Delay..................Auto
Ch2 WRCAS GNT-Chip Delay..................Auto
Ch2 Command to CS Delay...................Auto