TLB bug... did it ever affect anybody?

[saaya]

Hey guys,

i just wondered... did anybody actually experience problems before flashing to a bios that contained the microcode update to fix the tlb bug? i havent really heard from anybody... and seeing as this tlb fix reduces perf quite a lot in some situations... wouldnt it make sense to not use it?

would be nice if we could disable the fix in bios right?
or is this possible already?

[Brother Esau]

The New DFI 790 Bios has it on by default but you can turn it off that is a option.....to bad the 12/11/07 Bios is Pure trash and probably does more harm then good

[saaya]

so its possible to NOT use the fix then? nice!
nobody replied so far... so i take it nobody had any stability issues without the tlb fix?

[KTE]

Have never had it yet at stock or up to 2.9GHz during gaming, WCG, P95 or any other bench. Every problem has mainly been AOD/BIOS/MB. But because the platform components have so many problems of their own yet people may start to attribute other errors as "the bug". It's a common thing in ignorance, I pondered it too.

If you experience it, you will experience it at stock too and only under very heavy loads.

[Cooper]

Have never had it yet at stock or up to 2.9GHz during gaming, WCG, P95 or any other bench.

+1

Tried two Phenoms on several boards

[Lightman]

Not experienced up to 2.5GHz...

At 2.6GHz though under Vista x32 I had blue screen with message saying something along the lines: Windows has not received interrupt from a second core in expected time...

That of course might be a typical Vista error if you're running unstable OC

I haven't played with Vista too much so I'm not sure

BTW new Gigabyte BIOS has Errata298 DISABLED by default and you can ENABLE it if you wish (is there anyone willing to do that?? )

[Oliverda]

.....to bad the 12/11/07 Bios is Pure trash and probably does more harm then good

Could you explain this detailed?

[JumpingJack]

Have never had it yet at stock or up to 2.9GHz during gaming, WCG, P95 or any other bench. Every problem has mainly been AOD/BIOS/MB. But because the platform components have so many problems of their own yet people may start to attribute other errors as "the bug". It's a common thing in ignorance, I pondered it too.

If you experience it, you will experience it at stock too and only under very heavy loads.

The wisdom of the thread ... truth of the matter, systems lock up for various reasons, trying to attribute to this specific bug would be difficult at best... as the other platform bugs get squashed, the rate of occurrence of any lockup would most likely not be anything noticable or outside the norm...

Most people would simply curse M$ anyway.... heck, the last round of 'Vista updates' wreaked havoc on one system, I had to go back with system restore 5 days just to get back to where I am day on day stable again.

[saaya]

Not experienced up to 2.5GHz...

At 2.6GHz though under Vista x32 I had blue screen with message saying something along the lines: Windows has not received interrupt from a second core in expected time...

That of course might be a typical Vista error if you're running unstable OC

sounds like one of your cores cant run 2.6ghz, check if you can find out which one, maybe the other cores can hit 2.8+ and you only have to keep one down at 2.5

well im starting to think this bug either only affects a small percentage of cpus, or it only happens in situations that none of us are ever going to get to. i mean if we dont run into any issues even when ocing then this bug cant be as bad as amd made it sound like.

wtg for hyping up this errata and scaring all your customers amd!

[Zertz]

I heard it was only under certain circumstances when all four cores are fully loaded with virtualization software...?

aka: it shouldn't happen to the vast majority

[JumpingJack]

I heard it was only under certain circumstances when all four cores are fully loaded with virtualization software...?

aka: it shouldn't happen to the vast majority

The explanation of Errata 298

The processor operation to change the accessed or dirty bits of a page translation table entry in the L2 from 0b to 1b may not be atomic. A small window of time exists where other cached operations may cause the stale page translation table entry to be installed in the L3 before the modified copy is returned to the L2. In addition, if a probe for this cache line occurs during this window of time, the processor may not set the accessed or dirty bit and may corrupt data for an unrelated cached operation. The system may experience a machine check event reporting an L3 protocol error has occurred. In this case, the MC4 status register (MSR 0000_0410) will be equal to B2000000_000B0C0F or BA000000_000B0C0F. The MC4 address register (MSR 0000_0412) will be equal to 26h

Virtualization exhaserbates the issue since the resource sharing will change context depending on loading of the cores. However, the actual errata can trigger just by running multithreaded code in which the page is labeled in correctly. This is part of a cache coherency problem and not restricted soley to virtualization.

What this basically is saying is that there are a few cycles between the time a page table is altered and the time the table is marked dirty. If a core grabs that shared memory (say a multithreaded program is using the same page table) before it is marked, then it will incorrectly load the wrong data into L3.

EDIT: But a strong point needs to be made.... that window of time is likely very small, so small that the probability of happening is slim to none ... this errata does not give cycles of time that it takes to update the TLB and even if it is 10's of cycles, it is such a small window, for typical DT usage one may never actually trigger it and if it does, the frequency of M$ blunders would overwhelm the signal.

[saaya]

thanks jumping jack for clarifying!

so this was overblown big time by amd and the press...
after all i dont even understand why amd made the tlb fix mandatory, that was really stupid... you basically slow down everybodies systems cause 0.01% has a problem... ts...

[Pianist]

I havent used it and been using my Phenom 9500 @ 2.6 for about 3 weeks now with no problem, I dont intend to ever patch it cause I know it wont ever be an issue lol.

[Syz`]

Run mine at 2.6Ghz 24/7, no errors here.

[Nedjo]

Thank you JumpingJack for another clarifying post.
This TLB issue was so overblown!

Did you ever look at ATI's and NVIDIA's "Readme"| files about driver issues with all drivers they're launching!

When you start reading what is still unsolved, and what can crash your system, you would never buy graphics card!

Competition used this "confession" of AMD and did some spinning with "friendly" media eventually creating the disastrous picture. Now, when dust is finally little settled, we can see how overblown this thing was.

[justapost]

Not experienced up to 2.5GHz...

At 2.6GHz though under Vista x32 I had blue screen with message saying something along the lines: Windows has not received interrupt from a second core in expected time...

I experienced that blue screen during 2008rc0 installation on xen. Win2k3 worked flawless.

[Lightman]

I experienced that blue screen during 2008rc0 installation on xen. Win2k3 worked flawless.

That's the one

Thanks! Now I know that Intel has TLB error as well (j/k)

[KTE]

Achim

Do you have HPET timer enabled in the BIOS?

[BeastNotro]

The only bug i have right now is this Dang Cold bug... Cough Cough, Sneeze Sneeze.. Dang Weather outside.

[metro.cl]

Maybe someone can tell how to make the bug appear, we have 2 configurations here, and have don over 2+ hours of continuous stress, with rendering, gaming, etc... and still no sign of it.

[KTE]

metro.cl: why would you want the bug to appear?

Let alone 2+ hours, I've done over 144 hours continuous without it at 2.42GHz CPU 1.98GHz NB/HT an Cooper must have done high hours too. If it doesn't appear for you, it just won't with desktop loads since P95 and FPU Julia is the heaviest desktop load I've seen yet possible.

[saaya]

how about linpack? did anybody try that yet?

[justapost]

Achim

Do you have HPET timer enabled in the BIOS?

No, it was recommended to disable HPET to run linux.

@saaya: had probs building linpack, might try later again.
Edit: Got it, runs without problems with a problem size of 20000 under denian/lenny (64bit).

[justapost]

That's the one

Thanks! Now I know that Intel has TLB error as well (j/k)

Well the error did not occure on a c2d laptop i had here for testing.
It occured only on the phenom system.

[KTE]

HPET Timer enabled is the cause of BSODs and instability for some people on Phenom/790FX. Just FYI.