Quote Originally Posted by eva2000 View Post
Clock Fine Delay At Work


Still very early into my testing of how memory behave on DFI LP LT X38-T2R with 11/28 bios. It basically seems like a more matured version of what is implemented on DFI LP UT P35-T2R

Playing with 2:3 divider (266/800) and 2x 1GB Crucial Ballistix PC2-8500, I found myself hitting memory clock wall at several points while doing my routine Memtest86+ v1.70 testing.

Only salvation to break through that memory clock wall was fine tuning Clock Fine Delay values for DIMM 1 & 3. To my surprise I broke through that 651Mhz wall and ended up at 666Mhz 5-5-5-9 at 2.49v being single Super Pi 32M stable!

  • 633mhz 5-5-5-9 at 2.27v was okay
  • 640mhz 5-5-5-9 at 2.31v was okay
  • 651mhz 5-5-5-9 regardless of vdimm used kept freezing in test #5 loop testing - clock fine delay was all set to Current.
  • 651mhz 5-5-5-9 at 2.38v errored out in memtest, but elimated freezing by increasing dimm 1 + 3 clock fine delay values from Current (2) to manually set 3.
  • 660mhz 5-5-5-9 at 2.45v was okay in memtest now by further increasing dimm 1 + 3 clock fine delay values from manually set 3 to 5.
  • 666mhz 5-5-5-9 at 2.49v would error out in test #5 loop on 2nd pass with a few errors everytime, no voltage adjustments helped.
  • 666mhz 5-5-5-9 at 2.49v was okay when i further increased dimm 1 + 3 clock fine delay values from manually set 5 to 6 or 7.
  • 670mhz 5-5-5-9 at 2.49v would error out in test #5 loop on 2nd pass with a few errors everytime, voltage adjustments didn't help much to stablise it. Dimm 1 + 3 clock fine delay values manually set at 7 helped reduce it to a few errors in memtest86+ v1.70 test #5 loop.


So here's where I end up at so far 666Mhz 5-5-5-9 at 2.49v! Pretty awesome for initially having hit a brick wall at 651Mhz 5-5-5-9!





nice one Eva! is it ok to push NB to 1.6v?