AMD issues STOP SHIP order on Barcelona

[JumpingJack]

And the plot thickens.....

http://www.techreport.com/discussions.x/13724

B3 not until Mid Q1 to Late Q1 2008 ... translation, early Q2

"Saucier confirmed to us that the test systems at the Tahoe press event did not have the workaround enabled. "

So that is clear.... what we saw is what we get. There was no baked in 10% performance hit because of some BIOS tweak.

@ Informal -- we both errantly thought Errata 254 was the bug... but it is not, if you read the link above, it is designated as Errata 298, which does not appear in AMD's errata publication.

This was bad news all around.

EDIT: Ohhh, goodness... it get's worse.... it is not clear if the data we observed two weeks ago is sane...

We tested at a 2.3GHz core clock with a 2.0GHz north bridge clock, because AMD told us those speeds were representative of the Phenom 9600. Our production samples of the Phenom 9500 and 9600, however, have north bridge clocks of 1.8GHz. We've already confirmed lower scores in some benchmarks.

Given everything we've learned in the past few days, our review clearly overstates Phenom 9600 performance, as do (more likely than not) other reviews of the product. We can't know entirely by how much, though, until we can test a Phenom system with the TLB erratum workaround applied.

The NB were not clocked to the models of interest, so the 2.3 and 2.2 GHz at stock are likely not representative of the retail chip.