Quote Originally Posted by Shintai View Post
If that was true, we would see whole other SSE scenarios on 1 and 2MB Core 2s. In short, you are wrong. And I´m pretty sure AMDs engineers would have done this already if there was a valid reason. But there aint. I know it would be nice if there was an easy killer solution. But it doesnt exist, period!
No, the reason AMD couldn't put more transistors (more cache) is because the barcelona is already consuming too much power @ 2.3 GHz (leakage) as it is. Their process technology has more leakage than Intel's at 65 nm. YOU are wrong about the cache, and you have not backed up your statement at all. Intel has put lots of cache on core 2 based cpu's because they CAN while remaining within their target TDP, and AMD CAN NOT. IMC does NOT alleviate the need for good/large caches to any significant degree. IMC helps in FAR LESS cases than a large and fast cache. The only good thing about K8/K10 is that the cores can communicate with each other at full speed, although it seems that isn't quite true either.