These are the rev 2's, I think you mean the B3 stepping.
Now... Intel, AMD or IBM for that matter can dial in higher clocks within process if they want, the problem is that they suffer from a huge fall off in yield or you can cherry pick the best of the best and push up higher that way.
At the end of the line the performance of the body or population of CPUs is normally distributed, see for example this paper:
http://eda.ee.ucla.edu/EE201A-04Spring/GIT-PV.pdf
All the variation from the processing, i.e. within die, die to die, wafer to wafer, even process step to process step ... leads to a normal distribution of performance when the device is finished (Fmax is bell shaped), there is a finite probability of getting die at the very far tail of that distribtion, unforunately that means very few actual die so 'cherry' pick. Unfortunately, you get so few you cannot make enough to go to market but you can make a few to show around to various HW sites and IT journalists to fool people into thinking you have a 3.0 GHz processor.
The other way, the yield killing way, is to specifically tune your lithography to make the gate length narrower... this drives up drive current and results in a higher probability of getting a fast clocking CPU, unfortunately 90% of your die get hosed... so again, you cannot make enough to go to market but you can make enough to show a few HW sites and IT journalists and as such fool people (investors) into thinking you can make 3.0 GHz parts.
I think, in light of the errata, we now understand why AMD would not let anyone benchmark those 3.0 GHz processors....
Jack
Bookmarks