K10 Folding@Home SMP Performance?

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sp33: I don't now a lot about F@H program itself. Could you please tell me if there is a "standard test molecule" in the program, which would mean that you both are running the same system? Or there isn't such a thing, and you both exchanged job IDs to run the same job? Or, the worst (and then useless) scenario, you both are using different jobs? :P

To the best of my knowledge, you mainly have to focus on the project #. The other run and gen stuff for the most part is irrelevent when doing comparison. I'm assuming this because I have around 10 P2653 WU that all ran at the same time, even though their run and gen number differ.

I wonder sometimes what the engineers of this chip were thinking when they designed this chip. This isn't derogatory either. I'm just wondering if we have another cell processor on our hands; a chip that is designed for a purpose outside the mainstream, such that only special programming will help it realize it's true potential. It is like ATI's latest GPU. On paper, it looked to be very well engineered. It works, and works well for the most part, but it seems as though there is a disconnect between the engineers and the programmers. Dunno, just some pondering on my part.

OT: I hope that F@H can be optimized to make the most of this processor. Perhaps the difference in times can be atributed to the L2 size? Again, if the L3 doesn't do the job, then it's going to hurt performance of the processor. If I'm correct, then Phenom does the opposite of Intel: pushing the data into L2 from the L3 in a more organized fashion while Intel pulls in from a larger L2 pool. Unless newer chipsets can improve the efficiency of the L3 somehow, then Core will outperform Phenom in F@H...

I know one reason why the K10 architecture isn't performing as great in Folding@Home, the cache. F@H loves big L2 cache, which most of the current Intel chips have at least 4MB and the Kentsfield with 8MB. F@H is really data intensive and the ability to fetch more and more instructions is key. However, it will be interesting to see if the Stanford Teams decides to exploit the K10 L3 and Integrated Memory Controller and optimize for that architecture.

The other reason could be Kyosen's results were ran on single-channel ram, which a while back, someone discovered that dual channel vs single channel ram has a big impact on performance. I think figures as high as 50% difference just by single and dual channel.

It'll come down to this:

Big L2 Cache vs IMC + L3 Cache