NextGen VS. CurrentGen CPU: 3DMark06

[mstp2009]

NB communicates to the CPU via HT, it's been this way since HT1.

But the L3 talks to memory, not the NB.

Sure you aren't looking at memory latency? Those latencies are horrible for a cache (even L3).

EDIT - I was referring to the first link which talks about ns time, fyi. The second one clearly shows cycles (which at 52 cycles is not pretty also).