And I was talking about IPC. IPC doesn't change significantly with memory speed you n00b.
Plus, with the 2MB L3 caches we see in K10, Phenom should be LESS limited by memory speed than K8 was (with it's relatively small caches). Once you increase cache size, memory interface speed becomes FAR LESS critical in determining performance, at least on 1 and 2P systems.
No, he was talking about ARCHITECTURE, not clockspeed.





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