Originally Posted by Motiv
Np, was looking at them thought people would like to see them. Thanks for posting the nice links
Np, was looking at them thought people would like to see them. Thanks for posting the nice links
Last edited by PhilDoc; 10-09-2007 at 09:29 AM.
Enrol yourself into our NEW CAMPAIGN !!!
It's Codenamed WFAL (pronounced Waffel) campaign and you'll love it
What do we do in our campaign?
We WFAL !!! Or WAIT FOR ACTUAL LAUNCH !!!!
Don't compare C2D and Barcelona, wait for launch of desktop parts this Nov/Dec.
Perkam
Enrol yourself into our NEW CAMPAIGN !!!
It's Codenamed WFAL (pronounced Waffel) campaign and you'll love it
What do we do in our campaign?
We WFAL !!! Or WAIT FOR ACTUAL LAUNCH !!!!
Don't compare C2D and Barcelona, wait for launch of desktop parts this Nov/Dec.
Perkam
Well, its called curiosity and there are a few server people on here.
Btw, you could use a spell checker.
I noticed this when it was published.
So, AMD K8 dual core 2.2GHz communicates between each core taking 53.5ns and the K10 quad core 2.0GHz communicates taking 76ns... according to those tests. And thus Netburst->Core 2 halved the previous latency while K8->K10 added ~50% to the latency...hmmm. Anyone else reproduce these tests?
Here was another Barcelona vs Harpertown short review: http://www.besttechreview.com/content.php?IndexID=750
This is an exact copy of an Anand article
http://www.anandtech.com/IT/showdoc.aspx?i=3099
As far as communication between cores. By definition of the program, memory systems would come into play and who knows how accurate the program is too begin with. Finally, I'm starting to feel like Perkam, this is just getting to be a little obsessive. Time to wait for the Phenom launch.
LOL! I've found 6 other articles in Eastern sites that were copied off ATs Barcelona reviews, word for word.
You know, I've felt fed up ever since September 10th, but I still want to see real numbers for fact. And I was only lurking on Opteron 2300 going by this thread. Phenom is yet far off IMO, and that only changes for me when someone gets one in their hand.As far as communication between cores. By definition of the program, memory systems would come into play and who knows how accurate the program is too begin with. Finally, I'm starting to feel like Perkam, this is just getting to be a little obsessive. Time to wait for the Phenom launch.
I've got one question tonight...
Ok, Barcellona uses HT1.0.
Phenom uses HT3.0
Phenom FX uses HT3.0
What about FASN8????????????
I was meaning no offense, just stating my own frustrationLOL! I've found 6 other articles in Eastern sites that were copied off ATs Barcelona reviews, word for word.
You know, I've felt fed up ever since September 10th, but I still want to see real numbers for fact. And I was only lurking on Opteron 2300 going by this thread. Phenom is yet far off IMO, and that only changes for me when someone gets one in their hand.
Non taken bro, don't worry.
this thread is the source of my frustration for the past couple of weeks... why can't asus get a working bios...
Core i7 920 3849B028 4.2ghz cooled by ek hf | 6gb stt ddr3 2100 | MSI HD6950 cf cooled by ek fc | Evga x58 e760 Classified | 120gb G.Skill Phoenix Pro | Modded Rocketfish case + 1200w toughpower | mcp 655 pump + mcr 320 + black ice pro II
Another question:
if I would build today a dual 23xx based opteron, with two processors, around 4Gb of RAM (that would possibly increase with time) and two HDs... What sort of PSU should I use? "How much power" it should have?
Thanks a lot.
Zippy 700, PCP&C 750?
Ryzen 9 3900X w/ NH-U14s on MSI X570 Unify
32 GB Patriot Viper Steel 3733 CL14 (1.51v)
RX 5700 XT w/ 2x 120mm fan mod (2 GHz)
Tons of NVMe & SATA SSDs
LG 27GL850 + Asus MG279Q
Meshify C white
Without a vid card, a class 400W is more than enough as you'll see in reviews for peak VAC consumption.
even considering two processors at once?
Thanks a lot, KTE.
Now, the only question for me is: what will be the HT version of FASN8?
Yep. The figures of around 260W sustained peak draw were dual socket Opty 2350 with 12x 15k SAS in RAID 0 using a RAID storage card and 8x1GB RAM (Disk, RAM and CPU being loaded). 400W 80%+ efficient PSU is roomy enough, unless you'll be adding vid card, in which case, a little higher is better (esp. if both oc'd).
No idea of FASN8 (that would require more power by design).
You're welcome
I assumed, that you refer to Johan's cache ping pong test. One of your later postings confirmed this. Well, I followed the development of this test on the original aceshardware forums a while ago and many ideas have been discussed back then. You can find the full discussion and an early version of the code here:
http://web.archive.org/web/200505281...0681&forumid=2
First I have to say, that this special test is referring to a special variant of core to core communication. And here I think, that K10 got a performance hit in this benchmark due to it's write buffering and maybe even L3 cache (which BTW adds ~20ns to mem latency in case of a miss). This benchmark doesn't tell us anything about how fast a core can access data in another core's cache, which was not written right before this access but at least tens of cycles earlier. Except for semaphores and the like such an access behaviour would just stand for a bad multithreaded coding style.
SSE(2) instructions are mostly being double decoded on K8. SSE was vector decoded on K7. Since these 2 separate ops for both register halves on K8 finished one half one cycle earlier than the other half, it led to a nice 4 cycle latency for standard ops (add, sub, mul).
But as pointed out in the past (google for "k8 sse bottleneck"), there was a strange behaviour regarding SSE loads as you can see in the tests here again. Maybe due to the double decode, it was necessary, that such a decoded instruction uses a single FP unit sequentially. While using x87 or MMX loads it was possible to load two 64 bit values per cycle, this was not true using aligned 128 bit loads resulting in 0.5 SSE loads/cycle. This has been solved (maybe simply by avoiding the double decoding) - leading to a quadrupled SSE load performance compared to K8.
Really enjoy your posts here, they're very informative and always a nice addition to the forumsI assumed, that you refer to Johan's cache ping pong test. One of your later postings confirmed this. Well, I followed the development of this test on the original aceshardware forums a while ago and many ideas have been discussed back then. You can find the full discussion and an early version of the code here:
http://web.archive.org/web/200505281...0681&forumid=2
First I have to say, that this special test is referring to a special variant of core to core communication. And here I think, that K10 got a performance hit in this benchmark due to it's write buffering and maybe even L3 cache (which BTW adds ~20ns to mem latency in case of a miss). This benchmark doesn't tell us anything about how fast a core can access data in another core's cache, which was not written right before this access but at least tens of cycles earlier. Except for semaphores and the like such an access behaviour would just stand for a bad multithreaded coding style.
SSE(2) instructions are mostly being double decoded on K8. SSE was vector decoded on K7. Since these 2 separate ops for both register halves on K8 finished one half one cycle earlier than the other half, it led to a nice 4 cycle latency for standard ops (add, sub, mul).
But as pointed out in the past (google for "k8 sse bottleneck"), there was a strange behaviour regarding SSE loads as you can see in the tests here again. Maybe due to the double decode, it was necessary, that such a decoded instruction uses a single FP unit sequentially. While using x87 or MMX loads it was possible to load two 64 bit values per cycle, this was not true using aligned 128 bit loads resulting in 0.5 SSE loads/cycle. This has been solved (maybe simply by avoiding the double decoding) - leading to a quadrupled SSE load performance compared to K8.
Has anyone tried it with registered RAM?
Opteron 165 0536MPMW @ 2850Mhz
Corsair Twinx2048-4000pt UCCC
Antec Smart Power 500
Scathe Ninja 120mm fan
Yes,for that matter no one out there got working boards Tyan, Super micro ???Originally Posted by cky2k6 View Post
this thread is the source of my frustration for the past couple of weeks... why can't asus get a working bios...
This hit inquirer
linkBARCELONA NEEDS HELP FAST.
Apparently Barcelona will not work in older Mainboards, OLDER Meaning Yesterday & Today & for some time, as it useS multiple voltages at same time, in core, so its input pins are also multiple ?, anyway, due to unique Voltages simultaneously in core, there are no Mainboards, AT ALL.
Testers Stuck Pair into tyan 29XX, No Go, took working system & stuck in Barcelona & 50% lower scores than opteron dual cores. Thats BIG PROBLEM, I think.
Maybe its simple Hardware Socket or just rewire/upgrade of controllers, YET What if Barcelona internal CROSSBARS are all tuned wrong to put out such slow output.
extra!!!extra:kb940520 tests redfiboost/butt locker. Get it ,,ha.ha.ha?ah.
Signed:PHYSICIAN THOMAS STEWART VON DRASHEK M.D..
posted by : THOMAS STEWART VON DRASHEK, 10 October 2007
This slowdown is handicapping the fanboys to brag about barc for least...
This was just someones comment about the new AMD roadmap that the inq posted. It was listed in the comments section. Who knows what validity it has.
Yes, its not news its a comment, point is all in all its a big lengthy delay,it holds the same validity as some one ranting in these forums.
But being a dual socket Opteron user its a frustrating experience.
my 2 cents
OEM's get their chips months or atleast weeks before launch but not able to see a decent working board after weeks of launch is the problem,forget about benchmarking and losing crown kind of stuff.
Stabilizing takes time its ok, but minimal working should not.
Problem is with board makers or BIOS writers or with barcs or combined ?
PS: Nothing against you Phil,its an AMD chip buyer/little fan frustration.
Maybe be true, but what I know is that we haven't seen one run correctly on this site. I suspect that the two main reviews that I have seen had them running correctly and I would imagine that there are AMD customers that have Barcelona systems running. I also believe that there are significant problems with the present platform.
I'm not sure what the problem is here, but I suspect its mainly because we're just a little farther down the food chain then Dell, etc. AMD's support is too busy stamping out fires elsewhere.
No offense to Dave, Steven, etc who have worked hard to give us some insight.
In the end, I do believe the writer is correct in sense that the present mb do not work well with K10 and we will not see the full potential of this cpu until new mb are designed. Unfortunately all of those who thought they could just buy the cpu will have to get a new mb as well. I'm glad I just upgraded my 939 and waited.
PS. No offense was taken and I'm frustrated as well
Last edited by PhilDoc; 10-10-2007 at 12:56 PM.
Hypothetical situation:
What if Barcelona is actually all it's cracked up to be, and a little more. What kind of demand would that cause for these chips? What if the supply couldn't fill demand, considering the HPC and supercomputer obligations AMD needs to fill first. My guess is the backlash from that would be as blown out of proportion as the situation now, if not worse.
I imagine AMD is ramping %110, and their first priorities are getting these chips into the hands of the big contractors who already signed for them. I'm sure that is much more important to them than worrying about keeping a handful of enthusiasts happy. After all, these are server and HPC chips.
Just, what if...!
The doom and gloom makes me
Oh, I'm not gloom and doom, just frustrated. You did notice that I said we wouldn't see the real potential of these chips until we had better mb. I meant that in a very positive way.Hypothetical situation:
What if Barcelona is actually all it's cracked up to be, and a little more. What kind of demand would that cause for these chips? What if the supply couldn't fill demand, considering the HPC and supercomputer obligations AMD needs to fill first. My guess is the backlash from that would be as blown out of proportion as the situation now, if not worse.
I imagine AMD is ramping %110, and their first priorities are getting these chips into the hands of the big contractors who already signed for them. I'm sure that is much more important to them than worrying about keeping a handful of enthusiasts happy. After all, these are server and HPC chips.
Just, what if...!
The doom and gloom makes me
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