thanks george, and thanks bill, looks like your eye surgery was well worth it

im leaving to yet another ln2 party for the weekend ^^
im taking a p5k3 with me and will check the stepping this weekend.
i compared 3 boards today and yesterday, interesting...

theres a difference of 50mhz between the best and the worst in regards to max clockspeed. same cpu, same bios, same settings.
theres something else that confused me.

remember the old board i always mentioned that only did 1825 max dc stable?
its one of the first retail p5k3... well now it does 1900+...
i switched the cpu and wham, suddenly it runs much better.

the weird thing is, before it was running with a 6600 that could run a high fsb.
now its running a 6750... im sure i checked the fsb stability of the 6600 by using the same fsb or higher with a different mem divider. and it was stable... so i assumed that fsb was stable... but for some reason the 6600 was not stable at the same fsb when i used the 1:2 mem divider.

and the difference between the dividers must be huge, because with the other divider i could run an fsb of 500 easily and it was stable.
with the 1:2 divider i was limited to 1825, which is 455fsb.

could this be correct?
a max fsb difference between memory dividers?
and not a small one but a whooping 50mhz?
im puzzled... ill see if i can reproduce this with the 6600.
or could it be some registers changing once you set a high mem clock?
so once you set a memspeed of 1800+ the chipset/board relaxes some timings or changes something automatically to make a higher fsb stable?
and for some reason this only helps with 1333fsb cpus and not at all or not so well with 1066cpus?
reminds me of the l12 bridge thing from socket a

people could push their nf2 boards to higher fsbs with the bridge mods... its just weird this time that the memory controller is limiting that much.
but in general thats very characteristically for p35 ddr3 in my experience so far, the chipset is very limited by the ddr3 mem controller.
we can reach a notably lower max fsb with p35 ddr3 compared to p35 ddr2, which i think its the ddr3 mem controller limiting.

maybe we should compare the registers with p35 ddr3 and p35 ddr3, maybe on a hybrid board ideally so only the registers important for ddr2 and ddr3 operations change. that way we could maybe find a trick to get the same high fsbs on p35 with ddr3 as with ddr2...