K10 Scores starting to surface

[metro.cl]

I'm not sure if that'll be updated at all for the Budapest or Shanghai. It might well contain information referring to them. I know back in 2006 Barcelona was supposed to have a dual DDR2 and DDR3 controller, but that only one could work on the board. However, AMD said that the latest K10 doesn't support DDR3, while the guides are revealing DDR3 plans alongside DDR2.

Shangai and Budapest will use DDR2 only.

First one with DDR3 will be Montreal and Suzuka

[Motiv]

I suppose that'll be true for AT and TR reviews too

Anand has said he used a B1 just for clarification

[dave_graham]

Interesting... VERY. Although it'll take me a year more to read.


4 HT links too. Hmm....

there are 4 HT links in each core.

23xx series have 1 fused out.
83xx series have all enabled.

cheers,

dave

[Lightman]

there are 4 HT links in each core.

23xx series have 1 fused out.
83xx series have all enabled.

cheers,

dave

That then means it is possible to build 8S system with only 1 hop to every socket.... Something I haven't been expecting before SocketF+ (G).

[dave_graham]

That then means it is possible to build 8S system with only 1 hop to every socket.... Something I haven't been expecting before SocketF+ (G).

some clarification.

for reference, AMD doesn't call anything F+. It's simply Socket L1 (Socket F) and Socket L1-SP (split-plane; what people are calling F+).

back to the HT links for a second.

there's still a 2 hop penalty since only 1 of the 2 intra-CPU links are coherent. the secondary link is simply used to pass traffic. As there has been no realistic testing on even the 23xx series to determine utilization of that second link (and even it's performance) it's still safe to assume that n-way configurations will need to be passed over the coherent links only and, as such, will still require two hops. I'll get confirmation of this when I can.

here's a quick and dirty illustration.

mem <-> CPU0 = CPU 1 <-> mem
|| ||
mem <-> CPU2 = CPU 3 <-> mem

does that make sense? one lane of each HT pair is coherent.

cheers,

dave

EDIT: F'ing software isn't lining my pipes up correctly....

[JumpingJack]

Barcelona on sale: http://www.staticice.com.au/cgi-bin/...q=Opteron+2350

You're probably right Desdenboy. Hardware can have many capabilities disabled although etched out perfectly to implement down the line. I'm pretty sure TDP is the current problem with various hardware speeds on K10.

BTW, I noticed how Anantech and TechReport never posted CPU-Z screenies, whereas its very rare for reviewers to not do that generally.

I suppose that'll be true for AT and TR reviews too, apart from the 2360 SE 2.5GHz part which'll most likely be a B2 step.

Anand posted a CPUID of the 2.5 GHz chip:
http://www.anandtech.com/cpuchipsets...spx?i=3092&p=2

[Donnie27]

HW prefetching was disabled because it can significantly impact the performance of those Intel processors on specjjbb.

dave

Sorry I missed this one, but was it turned back on for other tests?

[bingo13]

The big question is; how well will it overclock on air?

Any K10 overclocking results out there?

The B2s clock nicely on air, just cannot show results yet as the L1N64 replacement is still under NDA. As for the Phenoms, it is too early to tell based on the current core release, but the RD790 does a very nice job of overclocking a 6400+.

[dave_graham]

Sorry I missed this one, but was it turned back on for other tests?

unknown.

dave

[akaBruno]

The B2s clock nicely on air, just cannot show results yet as the L1N64 replacement is still under NDA. As for the Phenoms, it is too early to tell based on the current core release, but the RD790 does a very nice job of overclocking a 6400+.

Can't wait to see that.

[KTE]

Anand posted a CPUID of the 2.5 GHz chip:
http://www.anandtech.com/cpuchipsets...spx?i=3092&p=2

Thanks, forgot about that. Thats the B2 core, the code says it v.clearly. Should've been more clear - I'm wanting to see the CPUZ for the launch processors they all reviewed, which were B1s; like Coolaler forum, Daves, TechwareLabs, TechReports and Stephens.

This is the CPUZ string a B1 gives (missing the DR-B1 in the revision field, even though its Agena)

[JumpingJack]

Thanks, forgot about that. Thats the B2 core, the code says it v.clearly. Should've been more clear - I'm wanting to see the CPUZ for the launch processors they all reviewed, which were B1s; like Coolaler forum, Daves, TechwareLabs, TechReports and Stephens.

This is the CPUZ string a B1 gives (missing the DR-B1 in the revision field, even though its Agena)

Yeah ... CPUID still needs a little more work to get all the info correct, but F22 is B2 I do believe.

Jack

[Lightman]

some clarification.

for reference, AMD doesn't call anything F+. It's simply Socket L1 (Socket F) and Socket L1-SP (split-plane; what people are calling F+).

back to the HT links for a second.

there's still a 2 hop penalty since only 1 of the 2 intra-CPU links are coherent. the secondary link is simply used to pass traffic. As there has been no realistic testing on even the 23xx series to determine utilization of that second link (and even it's performance) it's still safe to assume that n-way configurations will need to be passed over the coherent links only and, as such, will still require two hops. I'll get confirmation of this when I can.

here's a quick and dirty illustration.


does that make sense? one lane of each HT pair is coherent.

cheers,

dave

EDIT: F'ing software isn't lining my pipes up correctly....

I made a mistake because 8S topology has 3 hops and 4S 2 hops

I through that Opties 22xx had 3 HT links with only 1 ccHT but Opties 82xx had 3 HT links with all 3 ccHT enabled.

4S fully connected with plenty of I/O using Opteron 82xx - 2 HOP

................I/O
.................|
...CPU1.--.CPU2
.....|..\........|
.....|.....\.....|
...CPU3.--.CPU4
.....|
....I/O

8S using Opteron 82xx as an example CPU8 needs 3 hops to get data from CPU7

................CPU1.--.CPU2.--.CPU3
................/.....\......|..../..........\
............../.........\....|./...............\
I/O.-.CPU7.............\/|................CPU8 - I/O
..............\....... ../...|.\............../
................\....../.....|.....\......../
...............CPU4.--.CPU5.--.CPU6


If Barcelona can use 4 ccHT links now then it's great for scaling 4S/8S systems, but I remember that this feature was on roadmaps only for 45nm HT3 enabled successor of Barcelona. Can you clarify that for me Dave??