Quote Originally Posted by Lightman View Post
That then means it is possible to build 8S system with only 1 hop to every socket.... Something I haven't been expecting before SocketF+ (G).
some clarification.

for reference, AMD doesn't call anything F+. It's simply Socket L1 (Socket F) and Socket L1-SP (split-plane; what people are calling F+).

back to the HT links for a second.

there's still a 2 hop penalty since only 1 of the 2 intra-CPU links are coherent. the secondary link is simply used to pass traffic. As there has been no realistic testing on even the 23xx series to determine utilization of that second link (and even it's performance) it's still safe to assume that n-way configurations will need to be passed over the coherent links only and, as such, will still require two hops. I'll get confirmation of this when I can.

here's a quick and dirty illustration.
mem <-> CPU0 = CPU 1 <-> mem
|| ||
mem <-> CPU2 = CPU 3 <-> mem
does that make sense? one lane of each HT pair is coherent.

cheers,

dave

EDIT: F'ing software isn't lining my pipes up correctly....