Quote Originally Posted by KTE View Post
I'm not sure if that'll be updated at all for the Budapest or Shanghai. It might well contain information referring to them. I know back in 2006 Barcelona was supposed to have a dual DDR2 and DDR3 controller, but that only one could work on the board. However, AMD said that the latest K10 doesn't support DDR3, while the guides are revealing DDR3 plans alongside DDR2.
It's probably similar to dual core support in the first K8s. The SRQ had the support in it and the docs documented that. But it took 2 years until dual cores, which finally were making use of this, appeared.

So the DDR3 support seems to be there, but either the package or the programmed fuses don't allow it to work. The S940 opteron dies also supported unbuffered DIMMs, but it wasn't programmed to be enabled and the package likely used some different routing.

Maybe even the FB-DIMM support is already there (at least somewhere in the NB), because adding something rather complex later would require a redesign, while having it at least in some alpha state even makes it possible to debug it already.

Remember Hyperthreading, 64 bit support in Prescott etc... (see http://www.chip-architect.com/). All these things appear to have existed in silicon available on the market, while nobody could use them.

And the 4 HT links in Barcelona were present on die plots and die photos from day one. Unfortunately they don't make use of the 4th one yet..